Fujitsu MB96300 series Hardware Manual page 297

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MB96300 Super Series Hardware Manual
Writing the same data as currently stored in the WDTCP register has no effect.
Writing the complementary data of the current WDTCP contents clears the Watchdog counter and replaces
the current value in the WDTCP register. To clear the Watchdog Timer the next time, the write data must be
complemented again every time (original data - complementary data - original data - complementary data...)
Writing any data to the WDTCP register that differs from the current register contents or the complementary
value causes a Watchdog reset.
The following figure shows an example of the Watchdog Timer operation in this mode.
Figure 11.3-1 Watchdog Timer operation in complementary mode
Watchdog
counter
value
WDTCP contents:
Write value to WDTCP:
Watchdog
counter
value
WDTCP contents:
Write value to WDTCP:
■ Watchdog Timer reset causes
A Watchdog Timer reset can be asserted in the following cases:
• The Watchdog Timer was not cleared within the selected interval.
• Invalid data was written to the WDTCP register.
• '0' was written to the enable bit of the clock which is used as source clock for the Watchdog Timer
(CKSR: RCE, MCE or SCE).
selected Watchdog interval
0
XX
55h
55h
55h
(start
(no
counter)
effect)
selected Watchdog interval
0
XX
33h
33h
(start
counter)
CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET
AAh
AAh
AAh
55h
(clear
(no
(clear
counter)
effect)
counter)
CCh
33h
CCh
(clear
(clear
counter)
counter)
Watchdog
reset
(overflow)
55h
XX
55h
(no
effect)
Watchdog
reset
(illegal value written)
33h
XX
CBh
(illegal
value)
289

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