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MB96300 Super Series Hardware Manual
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Stop mode
All oscillators including the RC oscillator are disabled in Stop mode, hence no clock stop detection is
possible.
If an interrupt is asserted in Stop mode, then the MCU changes to Run mode with the clocks specified in the
CKSR register. The transition to Run mode is delayed until the clock selected with the CKSR: SC1S[1:0] bits
is stabilized. The operation of the System Clock 2 is delayed until the clock selected with the CKSR:
SC2S[1:0] bits is stabilized.
Note:
The Clock stop detection reset function is disabled during these stabilization times to avoid an accidental
assertion of the reset during clock stabilization. This means there will be no Clock stop detection reset if
the clock failed during Stop mode or within the stabilization time of the oscillator.
Always set BOTH system clocks to RC clock (CKSR: SC1S[1:0] and SC2S[1:0] = "00") when changing
to Stop mode to avoid this situation. Changing CLKS1 or CLKS2 to Main, PLL or Sub clock after start in
RC clock mode will not be executed if the corresponding clock did not restart and hence could not set its
clock ready monitor bit. The software should detect this situation by a time-out condition using the RC
clock timer.
■ Clock stop detection reset and Watchdog timer
A Clock stop detection reset is also asserted when the Main or Sub clock fails while used as source for the
Watchdog timer. During clock stabilization (after Stop mode release) however this reset function is disabled.
CHAPTER 8 RESETS AND STARTUP
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