Fujitsu MB96300 series Hardware Manual page 720

CHAPTER 28 SOUND GENERATOR
■ Sound Generator Control Register (SGCRLn)
Figure 28.2-3 Configuration of the Sound Generator Control Register (SGCRLn)
7
S1
R/W R/W R/W R/W
R/W : Readable and writable
: Initial value
712
6 5 4 3 2 1 0
S0 TONE OE2 OE1 INTE INT ST
R/W R/W R/W R/W
MB96300 Super Series Hardware Manual
SGCRL
Initial value
0 0 0 0 0 0 0 0
B
bit 0
ST Start bit
0 Stop operation
1 Start operation
bit 1
Interrupt bit
INT
read
0 no interrupt
1 interrupt request
bit 2
INTE
Interrupt enable bit
0 Interrupt disabled
1 Interrupt enabled
bit 3
OE1 Amplitude output enable bit
0 General purpose pin
1 SGA Output enbaled
bit 4
OE2 Sound output enable bit
0 General purpose pin
1 SGO Output enabled
bit 5
TONE Tone output
0 Tone and PWM mixed
1 SGO output
bit 7 bit 6
S1 S0 Operation clock select
0 0 Peripheral clock CLKP2
0 1 1/2 Peripheral clock CLKP2
1 0 1/4 Peripheral clock CLKP2
1 1 1/8 Peripheral clock CLKP2
write
clear interrupt
no effect