Fujitsu MB96300 series Hardware Manual page 425

MB96300 Super Series Hardware Manual
Bits 11-10: Counter clock selection
CKS1 CKS0
0 0
0 1
1 0
1 1
Bit 9: PPG output mask selection
PGMS
0
1
When the PPG Output Mask Selection bit is set to "1", the PPG output can be clamped at "L" or "H"
regardless of the mode, cycle, and duty settings.
The output level can be specified using the Output Polarity Specification bit (PCN:OSEL).
Bit 8: Undefined
Write always 0. The read value is undefined. Read-modify write is not affected.
Bits 7-6: Trigger input edge selection
EGS1 EGS0
0 0
0 1
1 0
1 1
When EGS1=0 and EGS0=0, the PPG can only be triggered by PCNn:STRG. The triggers EN[3:0],
Reload timer and external triggers are disabled for PPGn.
The other settings of EGS1 and EGS0 effect only the triggers EN[3:0], Reload timer and external triggers.
Writing '1' to PCNn:STRG triggers the corresponding PPG independent of the setting of PCNn:EGS1
and PCNn:EGS0.
Bit 5: Interrupt request enable.
IREN
0
1
Bit 4: interrupt request flag
IRQF Read Operation
0 No interrupt request
1 Interrupt request
If the Interrupt Request flag (IRQF) equals "1" and writing "0" to the flag take place at the same time, the
setting of the Interrupt Request flag (IRQF="1") by hardware has higher priority.
Bit 3-2: Interrupt cause selection
IRS1 IRS0
0 0
0 1
1 0
Down Counter Count Clock Selection
Clock selected by CKSEL
Clock selected by CKSEL divided by 4
Clock selected by CKSEL divided by 16
Clock selected by CKSEL divided by 64
Operation
No output mask
Output mask (Output "L" level latched:OSEL="0")
Selected Edge
no edge selected, triggering of PPG only possible by PCNHn:STRG
Falling edge
Both edges (rising edge, or, falling edge)
Operation
Disable interrupt requests.
Enable interrupt requests.
Clear the Interrupt Request flag.
Software trigger or external trigger input
Counter borrow
The counter matches the duty value.
CHAPTER 16 PROGRAMMABLE PULSE GENERATOR
Rising edge
Write Operation
Writing "1" has no effect.
Selection
417