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MB96300 Super Series Hardware Manual
20.4.4
Reception and Transmission Data Register (RDRn/TDRn)
The reception data register (RDRn) holds the received data. The transmission data
register (TDRn) holds the transmission data. Both RDRn and TDRn registers are located
at the same address.
■ Reception and transmission data registers (RDRn/TDRn)
Figure 20.4-5 Transmission and reception data registers (RDRn/TDRn)
R/W: Readable and writable
n = 0...9 according to device ( Please refer to
the datasheet of the corresponding device)
●
Reception:
RDRn is the register that contains reception data. The serial data signal transmitted to the SINn pin is
converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7)
contains 0. When reception is complete the data is stored in this register and the reception data full flag bit
(SSRn:RDRF) is set to 1. If a receive interrupt request is enabled at this point, a receive interrupt occurs.
Read RDRn when the RDRF bit of the status register (SSRn) is 1. The RDRF bit is cleared automatically to 0
when RDRn is read. Also the receive interrupt is cleared if it is enabled and no error has occurred.
Data in RDRn is invalid when a reception error occurs (SSRn: PE, ORE, or FRE = 1).
7
6
5
4
3
2
1
R/W R/W R/W R/W
R/W
R/W
R/W R/W
0
RDRn/TDRn
Initial value
0 0 0 0 0 0 0 0
B
bit 7 to 0
R/W
Data Registers
Read
Read from Reception Data Register
Write
Write to Transmission Data Register
CHAPTER 20 USART
485
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