Fujitsu MB96300 series Hardware Manual page 323

F2mc-16fx 16-bit

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MB96300 Super Series Hardware Manual

external bus data

The following table describes the effect of the endian selection for different external bus formats:

Table 12.2-3 Endian selection

selected bus

width of the

internal bus

external bus

This bit selects the data width of the external bus for the corresponding address

• '0' - 16-bit data width selected.

• '1' - 8-bit data width selected.

• The initial value is '0'. BW of EACR[5] however is changed to '1' by the Boot

ROM program in case of an 8 bit wide external reset vector fetch, except om

MB96(F)38x at ext. Boot Vector fetch in non-multiplexed bus mode where BW

of EACR[4] is set to '1'.

little endian (ES = '0')

• WRH and WRL are both activated during any write access.

• UB and LB are both activated during any write and read access.

• The address is always even (A00 = '0')

• The internal 16 bit access is split into two 8 bit accesses:

1. Transfer AA: External address equals to internal address (A00= '0')

2. Transfer BB: External address incremented by 1 (A00= '1')

• WRL is activated during any write access, WRH is ﬁxed to '1'.

• LB is activated during any write and read access, UB is ﬁxed to '1'.

CHAPTER 12 EXTERNAL BUS INTERFACE

sequence on external bus

big endian (ES = '1')