Fujitsu MB96300 series Hardware Manual page 315

MB96300 Super Series Hardware Manual
Table 12.2-2 Function description of each bit of the External bus clock and Function register
Bit name
bit 12 CKI:
External bus clock
inverting
bit 13 CKE:
External bus clock
output enable
bit 14 RYE:
External Ready
function enable
bit 15 HDE:
Hold function enable
• This bit controls the active edge of the external bus clock.
• '0' - the inactive level is '0' and the rising edge is the active edge.
• '1' - the inactive level is '1' and the falling edge is the active edge.
• The initial value is '0'.
• The output of the external bus clock to the CLK-pin depends also on the CKE
and CSM bits.
• The setting of this bit influences only the output of the clock to the
corresponding pin, but not the internal function.
• This bit controls the output of the external bus clock signal pin (CLK).
• '0' - The external bus clock is not output to the corresponding pin. The CLK-
pin is controlled by the corresponding DDR-register.
• '1' - The external bus clock is output to the corresponding pin.
• The initial value is '0'.
• Do not enable the external bus clock before all other clock settings are
completed.
• This bit enables the external ready function of the external bus.
• '0' - external Ready function for all external areas is disabled.
• '1' - external Ready function for all external areas is enabled.
• The initial value is '0'.
• The input of the corresponding pin for RDY is not enabled by setting this bit.
This must be done by software in the Input enable register (PIER) and the Data
direction register (DDR) by setting the corresponding PIER to '1' and the DDR
to '0'.
• For a detailed description of the Ready function see chapter 12.3.1 "Ready
Function".
• This bit enables the Hold function of the external bus.
• '0' - Hold function is disabled.
• '1' - Hold function is enabled.
• The initial value is '0'.
• If the Hold function is enabled, the output of Hold Acknowledge pin (HAK) is
always enabled. The input of the corresponding pin of HRQ must be enabled
by Software in the Input enable register (PIER) and Data direction register
(DDR) by setting the corresponding PIER to '1' and the DDR to '0'.
• For a detailed description of Hold function see chapter 12.3.2 "Hold
Function".
CHAPTER 12 EXTERNAL BUS INTERFACE
Function
307