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CHAPTER 21 400 kHz I2C INTERFACE
Since there are separate registers for the ten and seven bit address and their bit masks, it is possible to make
the interface acknowledge on both addresses by setting the ENSB (in ISMK) and ENTB (in ITMK) bits. The
received slave address length (seven or ten bit) may be determined by reading the RAL bit in the ITMK
register (this bit is valid if the AAS bit is set only).
It is also possible to give the interface no slave address by setting both bits to "0" if it is only used as a
master.
All slave address bits may be masked with their corresponding mask register (ITMK or ISMK).
■ Slave address masking
Only the bits set to "1" in the mask registers (ITMK / ISMK) are used for address comparison, all other bits
are ignored. The received slave address can be read from the ITBA (if ten bit address received, RAL="1") or
ISBA (if seven bit address received, RAL="0") register if the AAS bit in the IBSR register is "1".
If the bit masks are cleared, the interface can be used as a bus monitor since it will always be addressed as
slave. Note that this is not a real bus monitor because it acknowledges upon any slave address reception, even
if there is no other slave listening.
■ Addressing slaves
In master mode, after a start condition is generated the BB and TRX bits are set to "1" and the contents of the
IDAR register is sent in MSB first order. After address data is sent and an acknowledge signal was received
from the slave device, bit 0 of the sent data (bit 0 of the IDAR register after sending) is inverted and stored in
the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR register. This
procedure also applies to a repeated start condition.
In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit
address header which consists of the bit sequence "1 1 1 1 0 A9 A8 0", it is followed by the second byte
containing the lower eight bits of the ten bit slave address (A7 to A0).
A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start
condition (SCC bit in IBCR) followed by a ten bit address header with read access (1 1 1 1 0 A9 A8 1).
Summary of the address data bytes:
7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0.
7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1.
10 bit slave, write access: Start condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0.
10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start -
1 1 1 1 0 A9 A8 1.
■ Arbitration
During sending in master mode, if another master device is sending data at the same time, arbitration is
performed. If a device is sending the data value "1" and the data on the SDA line has an "L" level value, the
device is considered to have lost arbitration, and the AL bit is set to "1." Also, the AL bit is set to "1" if a
start condition is detected at the first bit of a data byte but the interface did not want to generate one or the
generation of a start or stop condition failed by some reason.
Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave mode
so it is able to acknowledge if its own slave address is being sent.
■ Acknowledgement
Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR register can be used
to select whether to send an acknowledgment when data bytes are received.
When data is send in slave mode (read access from another master), if no acknowledgement is received from
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MB96300 Super Series Hardware Manual
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