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CHAPTER 6 CLOCKS
6.2.4
Clock Frequency Control Register (CKFCR)
The Clock Frequency Control Register (CKFCR) is used to control the Peripheral clock
dividers (1 and 2), the Bus clock divider and the RC oscillator frequency.
■ Configuration of the Clock Frequency Control Register (CKFCR)
Figure 6.2-5 shows the configuration of the Clock Frequency Control Register (CKFCR) and Table 6.2-4
describes the function of each bit.
The register can be accessed 16-bit wide (CKFCR) and 8-bit wide (low byte: CKFCRL, high byte:
CKFCRH).
Figure 6.2-5 Configuration of the Clock Frequency Control Register (CKFCR)
Address:
15
14
13
000404
H
PC2D3 PC2D2 PC2D1 PC2D0 PC1D3
000405
H
R/W R/W R/W R/W R/W
X
: undefined value
R/W
: Readable and writable
: Initial value
160
12
11
10
9
8
7
PC1D2 PC1D1 PC1D0
BCD3 BCD2
R/W R/W R/W
R/W R/W R/W R/W
BCD3
bit11
PC1D3
bit15
PC2D3
6
5
4
3
2
1
BCD1 BCD0
-
-
-
-
-
-
bit0
RCFS
0
Nominal RC clock frequency set to 100kHz
1
Nominal RC clock frequency set to 2MHz
bit1 - bit3
-
0
Always write "0" to these bits
bit7
bit6
bit5
bit4
BCD2
BCD1
BCD0
0
0
0
0
0
0
0
1
...
...
...
...
1
1
1
1
bit10
bit9
bit8
PC1D2
PC1D1
PC1D0
0
0
0
0
0
0
0
1
...
...
...
...
1
1
1
1
bit14
bit13
bit12
PC2D2
PC2D1
PC2D0
0
0
0
0
0
0
0
1
...
...
...
...
1
1
1
1
0
Initial value
0 0 0 0 0 0 0 0 0 0 0 0 X X X 1
RCFS
R/W
RC Clock Frequency Select bit
Reserved
Bus Clock Division select bits
CLKB is CLKS1 (divided by 1)
CLKB is CLKS1 divided by 2
CLKB is CLKS1 divided by BCD[3:0]
CLKB is CLKS1 divided by 16
Peripheral Clock 1 Division select bits
CLKP1 is CLKS1 (divided by 1)
CLKP1 is CLKS1 divided by 2
CLKP1 is CLKS1 divided by PC1D[3:0]
CLKP1 is CLKS1 divided by 16
Peripheral Clock 2 Division select bits
CLKP2 is CLKS2 (divided by 1)
CLKP2 is CLKS2 divided by 2
CLKP2 is CLKS2 divided by PC2D[3:0]
CLKP2 is CLKS2 divided by 16
B
+ 1
B
+ 1
B
+ 1
B
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