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16.4 Operation of I
2
The I
C bus establishes communication via two duplex bus lines, one serial data line
(SDA) and one serial clock line (SCL). The I
(SDA and SCL) to make the wiring possible.
I I
2
C interface operation
❍ Start conditions
When the MSS bit is set to 1 while the bus is open (BB=0, MSS=0), the I2C interface is put in
master mode and generates a start condition. Even if the bus is being used (BB=1) in master
mode, another start condition can be generated by setting the SCC bit to 1.
Start conditions can be generated in the following two ways.
•
Setting the MSS bit to 1 by writing when the bus is not used (MSS=0, BB=0, INT=0, AL=0).
•
Write 1 to the SCC bit in interrupt state when the bus is in master mode (MSS=1, BB=1,
INT=1, AL=0).
If the MSS bit is set to 1 by writing when another system (idling) is using the bus, the AL bit is
set to 1. Any attempt other than as described above to set the MSS and SCC bits to 1 is not
effective.
❍ Stop conditions
If the MSS bit is set to 0 by writing in master mode (MSS=1), a stop condition is generated and
the I2C interface is put into slave mode.
Stop conditions are generated under the following conditions:
•
Setting the MSS bit to 0 by writing interrupt state when the bus is in master mode
(MSS=1,BB=1,INT=1,AL=0).
•
Any attempt other than as described above to set the MSS bit to 0 is ignored.
❍ Addressing
In master mode, after a start condition is generated, the I2C interface is set to BB=1 and
TRX=1, and the contents of the IDAR register are output, starting from the MSB. If Acknowledge
is received from the slave after address data is transmitted, bit 0 of the transmitted data (bit 0 of
the posttransmission IDAR register) is set to the other value, which is stored in the TRX bit.
In slave mode, after a start condition is generated, the I2C interface is set to BB=1 and TRX=0,
and the data transmitted from the master is received by the IDAR register. After the address
data is received, the contents of the IDAR register are compared with those of the IADR
register. If both values match, AAS=1 is set and Acknowledge is transmitted to the master.
Then, the value of bit 0 of the received data (bit 0 of the postreception IDAR register) is stored in
the TRX bit.
2
C Interface
2
C interface has two open-drain input pins
2
CHAPTER 16 I
C INTERFACE
359
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