Fujitsu MB96300 series Hardware Manual page 391

F2mc-16fx 16-bit

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MB96300 Super Series Hardware Manual

16-bit Output Compare Operation

In the 16-bit Output Compare operation, an interrupt request ﬂag can be set and the

output level can be toggled when the speciﬁed compare register value matches the 16-bit

free-run timer value. The CMOD0 and CMOD1 bits can be used to deﬁne the

corresponding compare registers for each pin.

■ Sample output waveform when CMOD[1:0] = "00

When CMOD[1:0] = "00

every match with the register value. Each output value is controlled by one compare register.

OUT0: The level is only reversed by a match with compare register 0.

OUT1: The level is only reversed by a match with compare register 1.

Figure 14.4-6 Sample of output waveform when CMOD[1:0] = "00

Counter value

Note: In this figure, the initial value is "0" for both pins.

■ Sample output waveform with two compare registers when CMOD[1:0] = "01

When CMOD[1:0] = "01

upon every match with the register value. This is identical to the behavior for CMOD[1:0] = "00

However, the output level of the second pin is reversed upon a match with either compare register 0 or

compare register 1 (3). This allows to define a pulsed signal with one edge defined by the value in compare

the same value, the operation is identical to the case for CMOD[1:0] = "00

A pulse width modulated signal with differing frequency can be defined by using this mode together with the

reset option by compare register match for the Free-Running Timer (MODE-bit in TCCSLx registers).

OUT0 (2): The level is only reversed by a match with compare register 0 (2).

", the output level of the pin corresponding to the compare register is reversed on

", the output level of the pin corresponding to compare register 0 (2) is reversed

CHAPTER 14 16-BIT I/O TIMER