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CHAPTER 8 RESETS AND STARTUP
8.5.3
Clock Input and LVD Control Register (CILCR)
The Clock Input and LVD Control Register (CILCR) is used to control additional functions
of the oscillator circuit and the Low Voltage Detection Level.
■ Configuration of the Clock Input and LVD Control Register (CILCR)
Figure 8.5-4 shows the configuration of the Clock Input and LVD Control Registers (CILCR) and Table 8.5-
4 describes the function of each bit.
The register can be accessed 16-bit wide (VRCR) and 8-bit wide (low byte: VRCR, high byte CILCR).
Figure 8.5-4 Configuration of the Clock Input and LVD Control Register (CILCR)
15
14
13
Address:
00042D
-
-
H
-
-
X
: undefined value
R/W
: Readable and writable
: Initial value
218
12
11
10
9
8
-
FCI
LVL3
LVL2
LVL1
LVL0
R/W R/W
R/W R/W R/W
-
MB96300 Super Series Hardware Manual
Figure 8.5-5
Initial value
X X X 0 0 0 0 0
B
bit11
bit10
bit9
bit8
LVL3
LVL2
LVL1
LVL0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
bit12
FCI
Fast Clock Input Select
0
Oscillation mode
1
Fast external clock input mode
bit15-13
-
Reserved
110
Always write "110" to these bits.
* Note: For the allowed settings and the analog detection level, please refer to
Low voltage detector level
Level 0 *
Level 1 *
Level 2 *
Level 3 *
Level 4 *
Level 5 *
Level 6 *
Level 7 *
Level 8 *
Level 9 *
Level 10 *
Level 11 *
Level 12 *
Level 13 *
Level 14 *
Level 15 *
the datasheet.
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