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MB96300 Super Series Hardware Manual
■ Clock modulator control register contents
Table 7.2-1 Function of each bit of the clock modulator control register (1/2)
Bit name
bit 0
PDX:
Power down bit
bit 1
MODEN:
Modulation
enable bit
"0": Power down mode
"1": Power up
• PDX is the power down signal for the modulator. Before the modulation can be
enabled, this bit must be set to 1 and the startup time of 6 µs must be awaited. Please
refer to the application note for a description of the recommended startup sequence.
• Before switching to power down mode (PDX=0), the modulator must be disabled ->
MODEN=0 and MODRUN=0.
"0": Modulation disabled.
"1": Modulation enabled.
• To enable the modulation, MODEN must be set to 1.
• Before the modulation can be enabled, the PLL must deliver a stable reference clock
(PLL lock time must be elapsed).
• The specified PLL frequency range for modulation is 16 MHz to
• Each PLL output frequency offers a set of possible modulation parameters. The
selected setting (CMPR register) and the PLL frequency must match.
Please refer to the CMPR register description.
• Whenever the PLL output frequency is changed or the PLL is switched off e.g. in
power down modes, the modulator must be disabled before -> MODEN=0 and
MODRUN=0.
• Before the modulation can be enabled, the modulator must be switched from power
down to active mode by setting PDX to 1 and the startup time of 6 µs must be
awaited.
Please refer to the application note for a description of the recommended startup
sequence.
• Before the modulation can be enabled, a proper setting must be selected via the
parameter register CMPR.
• After enabling the modulation by setting MODEN to 1, the modulator is calibrated.
During this time, the clock is unmodulated. Therefore the output clock does not
switch immediately to modulated clock. The status of the clock (frequency
modulated / unmodulated) is indicated by the MODRUN status bit. Please refer to
the MODRUN bit description.
• Due to the synchronization of the MODEN signal and the synchronized switching to
unmodulated clock, it takes less than 9 x T0 (input clock period) before the clock
switches to unmodulated clock after the modulation is disabled. The modulation can
be disabled at any time.
• Before changing the parameter register CMPR, the modulation must be disabled ->
MODEN=0 and MODRUN=0.
CHAPTER 7 CLOCK MODULATOR
Function
64
MHz.
183
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