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MB96300 Super Series Hardware Manual
*: Arbitration lost is detected within 3-bit time after setting the MSS bit to "1".
●
Example of occurrence of an interrupt (INT bit = 1) upon detection of "AL bit = 1"
When an instruction which generates a start condition is executed (setting the MSS bit to 1) with "bus busy"
detected (BB bit = 1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL bit = 1".
Figure 21.2-6 Diagram of timing at which an interrupt upon detection of "AL bit = 1" occurs
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
Master mode setting
Setting "1" to MSS bit in bus control register (IBCR)
Wait for the time for three-bit data transmission at the I2C
transfer frequency set in the clock control register (ICCR).*
BB bit =0 and AL bit = 1
Setting EN bit to "0" and initializing of I
Start Condition
Interrupt at 9th clock.
SLAVE ADDRESS
CHAPTER 21 400 kHz I2C INTERFACE
YES
2
C
ACK
DAT
AL bit clear on soft
INT bit clear on soft
and open SCL
NO
To normal process
557
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