Register Description - Fujitsu MB96300 series Hardware Manual

MB96300 Super Series Hardware Manual
22.3

Register Description

This section lists the CAN registers and describes the function of each register in detail.
■ Programmer's Model
The CAN module allocates an address space of 256 bytes (64 words). The CAN registers can be accessed
from the CPU in byte and word.
The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM. They buffer
the data to be transferred to and from the RAM, avoiding conflicts between CPU accesses and message
reception/transmission.
If several CAN modules are present on a device then they are located linearly in the address space with a
constant offset of 256 bytes. Please refer to the data sheet for the base address of each CAN module on the
device.
Table 22.3-1 CAN Register Summary
Offset
CANn base address + 0x0
CANn base address + 0x1
CANn base address + 0x2
CANn base address + 0x3
CANn base address + 0x4
CANn base address + 0x5
CANn base address + 0x6
CANn base address + 0x7
CANn base address + 0x8
CANn base address + 0x9
CANn base address + 0xA
CANn base address + 0xB
Byte Register Word Register
Name Name
CTRLRLn CTRLRn
CTRLRHn
STATRLn STATRn
STATRHn
ERRCNTLn ERRCNTn
ERRCNTHn
BTRLn BTRn
BTRHn
INTRLn INTRn
INTRHn
TESTRLn TESTRn
TESTRHn
CHAPTER 22 CAN CONTROLLER
Description
CAN n - Control register
CAN n - Control register
(reserved)
CAN n - Status register
CAN n - Status register
(reserved)
CAN n - Error Counter
(Transmit)
CAN n - Error Counter
(Receive)
CAN n - Bit Timing
Register
CAN n - Bit Timing
Register
CAN n - Interrupt
Register
CAN n - Interrupt
Register
CAN n - Test Register
CAN n - Test Register
(reserved)
Initial value
000X0001
XXXXXXXX
00000000
XXXXXXXX
00000000
00000000
00000001
X0100011
00000000
00000000
000000XX
XXXXXXXX
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