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CHAPTER 27 I
C INTERFACE (ONLY MB90485 SERIES)
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27.5 I
C Interface Operation
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The I
C bus performs communication using two bidirectional bus lines that consist of
one serial data line (SDA) and one serial clock line (SCL). The I
two open drain input/output pins (SDA, SCL) that allow hard-wired logic to be used.
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Start condition
If the bus is open (BB = 0, MSS = 0) and the MSS bit is set to "1", the I
master mode and the start condition is generated as well. Even if the bus is active (BB = 1) in
master mode, the start condition will be generated again if the SCC bit is set to "1". There are
two ways to generate the start condition:
•
In the state where the bus is not used (MSS = 0 & BB = 0 & INT = 0 & AL = 0), setting of the
MSS bit to "1"
•
In interrupt state and bus master mode (MSS = 1 & BB = 1 & INT = 1 & AL = 0), setting of
the SCC bit to "1"
If the MSS bit is set to "1" when another system uses the bus (in idle state), the AL bit is set to
"1". In states other than the above, setting the MSS bit and SCC bit to "1" is ignored.
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Stop condition
If the MSS bit is set to "0" in master mode (MSS = 1), a stop condition is generated and the
devices enter slave mode. A stop condition is generated when the following conditions exist:
•
If the MSS bit is set to "0" in bus master mode and in interrupt state (MSS = 1 & BB = 1 &
INT = 1 & AL = 0).
In the other modes, setting the MSS bit to "0" is ignored.
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Addressing
If, in master mode, a start condition is generated by setting BB = 1 and TRX = 1, the contents of
the IDAR register are output starting with the MSB. When, after the address data has been
transmitted, acknowledge is received from the slave, the TRX bit is set to the opposite value of
bit0 for the transmitted data (IDAR register: bit0 after transmission).
In slave mode, after a start condition is generated by setting BB = 1 and TRX = 0, transmitted
data from the master is received in the IDAR register. After the address data has been received,
the IDAR register and IADR register are compared. If the contents of these registers match,
AAS is set to "1", and acknowledge is transmitted to the master. Next, the TRX bit is set to the
same value as bit0 of the received data (IDAR register: bit0 after reception).
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Arbitration
If, when a master transmits, another master transmits data at the same time, arbitration occurs.
If the signal of the locally transmitted data represents "1" and the data on the SDA line is
represented by the "L" level, AL is set to "1" on the assumption that local arbitration is lost. As
previously described, AL is set to "1" when a start condition occurs, even though the bus is
active at the time. Setting AL to "1" results in MSS = 0 and TRX = 0, and the device enters slave
reception mode.
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C interface has instead
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C interface enters
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