Fujitsu MB96300 series Hardware Manual page 600

F2mc-16fx 16-bit

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CHAPTER 22 CAN CONTROLLER

Bit Timing Register (BTRn)

The Bit Timing Register (BTRn) enables controlling of the CAN bus controller bit timing.

■ Bit Timing Register (BTRn)

Figure 22.5-4 Conﬁguration of the Bit Timing Register (BTRn)

Bit Timimg Register high byte

Address : Base + 0x07

Bit Timing Register low byte

Address : Base + 0x 06

■ Function of the Bit Timing Register (BTRn)

[bit114 - bit12]

[bit11 - bit8]

[bit5 - bit0]

With a peripheral clock CLKP2 frequency of 8 MHz, the reset value of 0x2301 configures the CAN for a

bit rate of 500 kBit/s. The registers are only writable if bits CCE and INIT in the CAN Control Register

Read/write ⇒

(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Default value⇒

Read/write ⇒

(R /W ) (R/W) (R/W) (R/W) (R/W) (R/W) (R /W ) (R /W )

Default value⇒

Reserved bit

Always write "0". Read value is not deﬁned. Read-Modify-Write is not affected.

The time segment after the sample point

Valid values for TSEG2 are [ 0 ... 7 ]. The actual interpretation by the hardware of this value is such that one more

than the value programmed here is used.

The time segment before the sample point

Valid values for TSEG1 are [ 1 ... 15 ]. The actual interpretation by the hardware of this value is such that one more

than the value programmed here is used

(Re)Synchronisation Jump Width

Valid programmed values are 0-3. The actual interpretation by the hardware of this value is such that one more

than the value programmed here is used.

Baud Rate Prescaler

The value by which the peripheral clock CLKP2 frequency is divided for generating the bit time quanta. The bit time

is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are[0 ... 63]. The actual interpre-

tation by the hardware of this value is such that one more than the value programmed here is used.

MB96300 Super Series Hardware Manual