Fujitsu MB96300 series Hardware Manual page 719

F2mc-16fx 16-bit
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MB96300 Super Series Hardware Manual
Table 28.2-1 Function of each bit of the Sound Generator Control Register (SGCRHn)
Name
bit 10
FSEL: PWM
counter switching
bit
bit 9
BUSY:
Busy bit
bit 8
DEC:
Auto-decrement
enable bit
This bit switches the count value of the PWM counter between 256 and 384. Stop
operation when switching the count value. After FSEL is switched, set the amplitide
data, frequency data, decrement grade and tone register again.
0: 384 count
1: 256 count
This bit indicates whether the Sound Generator is in operation. This bit is set to "1"
upon the ST bit is set to "1". It is reset to "0" when the ST bit is reset to "0" and the
operation is completed at the end of one tone cycle. Any write instructions performed
on this bit has no effect.
The DEC bit is prepared for an automatic degradation of the sound in conjunction
with the Decrement Grade Register.
If this bit is set to "1", the stored value in the Amplitude Data Register is decremented
by 1(one), every time when the Decrement counter counts the number of tone pulses
from the toggle flip-flop specified by the Decrement Grade register.
CHAPTER 28 SOUND GENERATOR
Function
711

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