Main Clock Timer - Fujitsu MB96300 series Hardware Manual

F2mc-16fx 16-bit

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CHAPTER 10 SOURCE CLOCK TIMERS

Main Clock Timer

The Main clock timer consists of a 23-bit counter and a control register. The 23-bit

counter divides the Main clock CLKMC. The Main clock timer issues interrupts at

speciﬁed intervals based on carry signals of the Main clock counter.

■ Outline of the Main clock timer

A Power reset or a falling edge at the RST input pin initializes the Main clock timer to zero. The Main clock

timer is also initialized when the Main clock is disabled (at transition to Stop mode or by setting MCE to

"0"), or by writing "0" to the MCTR bit of the MCTCR register. The Main clock timer continues counting as

long as the Main clock is supplied. The Main clock timer is used to measure the Main clock stabilization wait

time and can be used to generate interval interrupts.

■ Block diagram of Main clock timer

Figure 10.3-1 shows a block diagram of the Main clock timer.

Main clock counter

counter reset

RST falling edge

Main oscillator disable

Main clock stop detection reset

Main clock timer interrupt signal

Figure 10.3-1 Block diagram of Main clock timer

CKSSR: MCST[2:0]

reset circuit

Main clock timer control register

MB96300 Super Series Hardware Manual

Main clock stabilization

time selector

Main clock timer interrupt

interval selector

Main Clock ready

Monitor (MCM)