Fujitsu MB96300 series Hardware Manual page 427

F2mc-16fx 16-bit
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MB96300 Super Series Hardware Manual
PPG0 to PPGn as selected are activated when the edge specified by the Trigger Input Edge Selection bits
(PCNn:EGS[1:0]) are detected by the specified activation trigger.
■ General Control Register 2 (GCN2g)
The General Control Register 2 (GCN2x) generates internal trigger levels using software for a PPG block of
4 PPGs.
GCN2Hg
Initial value:
GCN2Lg
Initial value:
R/W : Readable and writable
x
: undefined
Bits 15-12: Undefined
Always write "0". The read value is undefined. Read-modify-write is not affected.
Bits 11-8: Prescalar input selection
CKSEL0..3
0
1
Bits 7-4: Undefined
Always write "0". The read value is undefined. Read-modify-write is not affected.
Bit 3-0: EN trigger input
EN0..3
0
1
Set the levels of internal triggers EN0, EN1, EN2 and EN3.
If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits
(GCN1g:TSEL0[3:0], GCN1g:TSEL1[3:0], GCN1g:TSEL2[3:0], and GCN1g:TSEL3[3:0]) of PPGn,
then the selected EN serves as a PPG trigger input bit.
If the state selected with the trigger input edge selection bit (EGS[1:0]) is generated by software using the
trigger input bit (selected EN0, EN1, EN2, or EN3), the choice serves as an activation trigger to activate
the PPG.
■ PPG Cycle Setting Register (PCSRn)
The PPG Cycle Setting Register (PCSRn) controls the cycle of the PPG.
Figure 16.2-4 General Control Register 2 (GCN2g)
15
14
13
12
-
-
-
-
Access:
R/W0 R/W0 R/W0 R/W0 R/W
x
x
x
x
7
6
5
4
-
-
-
-
Access:
R/W0 R/W0 R/W0 R/W0 R/W
x
x
x
x
Use CLKP1 as prescaler input
Internal Triggers EN0, EN1, EN2, and EN3
CHAPTER 16 PROGRAMMABLE PULSE GENERATOR
11
10
9
8
CKSEL3 CKSEL2 CKSEL1 CKSEL0
R/W
R/W
R/W
0
0
0
0
3
2
1
0
EN3
EN2
EN1
EN0
R/W
R/W
R/W
0
0
0
0
Operation
Use RLT6 as prescaler input
Set the level to "L".
Set the level to "H".
419

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