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Table 34.2-1 ROM Control/Status register (MFMCS)
Bit name
bit 9 -
bit 11
bit 12
bit 13
bit 13 -
bit 15
■ ROM Timing Configuration register 0 (MFMTC0)
In the description below, the bit described in grey do exist in the ROM interface and indicate thus the
compatibility with the Flash interface. In case of a ROM, those bits have no functionnality.
-
•
Only available for compatibility with Flash interface but without func-
tionallity. Any values can be writen here.
CRBE
•
This bit enables/disables the code read buffer
•
Setting this bit to '1' enables the code read buffer. A code read ac-
cess from any address stores the complete 32-bit read data in a buff-
er. A later CPU read access to the address of the buffered data will
be executed without wait cycles and served by the buffer.
•
Setting this bit to '0' disables the code read buffer. Data is always
read directly from ROM.
•
The initial value of this bit is '1'.
DRBE
•
This bit enables/disables the data read buffer
•
Setting this bit to '1' enables the data read buffer. A data read access
from any address stores the complete 32 bit read data in a buffer. A
later CPU read access to the address of the buffered data will be ex-
ecuted without wait cycles and served by the buffer.
•
Setting this bit to '0' disables the data read buffer. Data is always
read directly from ROM.
•
The initial value of this bit is '1'.
-
•
Only available for compatibility with Flash interface but without func-
tionallity. Any values can be writen here.
CHAPTER 34 MASK-ROM MEMORY INTERFACE
Function
893
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