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CHAPTER 22 CAN CONTROLLER
22.8.1
Interrupt Register (INTRn)
The Interrupt Register (INTRn) points to the pending interrupt of highest priority.
■ Interrupt Register (INTRn)
Figure 22.8-1 Configuration of the Interrupt Register (INTRn)
Interrupt Register high byte
Address : Base + 0x08
Interrupt Register low byte
Address : Base + 0x 09
■ Function of the Interrupt Register (INTRn)
(For 32 message buffer CANs)
INTID15-0
0x0000
0x0001-0x0020
0x0021-0x7FFF
0x8000
0x8001-0xFFFF
(For 128 message buffer CANs)
INTID15-0
0x0000
0x0001-0x0080
0x0081-0x7FFF
0x8000
0x8001-0xFFFF
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the
highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has
cleared it. If IntId is different from 0x0000 and IE is set, the interrupt line to the CPU is active. The interrupt
line remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
The Status Interrupt has the highest priority. Among the message interrupts, the Message Object's interrupt
priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object's INTPND bit. The Status Interrupt is cleared
by reading the Status Register.
612
15
14
H
Read/write ⇒
(R)
(R)
(0)
(0)
Default value⇒
7
6
H
Read/write ⇒
(R)
(R)
(0)
(0)
Default value⇒
Interrupt Identifier (the number here indicates the source of the interrupt)
No interrupt is pending.
Number of Message Object which caused the interrupt.
unused.
Status Interrupt.
unused.
Interrupt Identifier (the number here indicates the source of the interrupt)
No interrupt is pending.
Number of Message Object which caused the interrupt.
unused.
Status Interrupt.
unused.
MB96300 Super Series Hardware Manual
13
12
11
10
9
INTID15-8
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
INTID7-0
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
⇐ Bit no.
8
INTRH
(R)
(0)
⇐ Bit no.
1
0
INTRL
(R)
(0)
(0)
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