Fujitsu MB96300 series Hardware Manual page 502

CHAPTER 20 USART
20.4.8 Extended Serial Interrupt Register (ESIRn)
The extended serial interrupt register contains control bits to change the interrupt
handling of the USART for improved interrupt handling and to enable DMA to handle
USART data transfers.
■ Extended serial interrupt register (ESIRn)
Figure 20.4-9 Configuration of the extended serial interrupt register (ESIRn)
R/W
X
-
Table 20.4-7 Function of each bit of the extended serial interrupt register (ESIRn)
Bit name
bit7 to -
bit4
494
7 6 5 4 3 2 1
TDRE RDRF RBI
-
- - - R/W R/W R/W
: Readable and writable
: Indeterminate
: Undefined
: Initial value
• These bits are undefined.
• Always write "0". Read-modify-write is not affected.
MB96300 Super Series Hardware Manual
0
ESIRn
Initial value
AICD
X X X X 1 0 X 0
B
R/W
bit 0
AICD Auto Interrupt Clear Disable
0 Auto Interrupt Clear is enabled (DMA can not be used)
1 Auto Interrupt Clear is disabled (DMA can be used)
bit 1
RBI Reception Bus Idle (sticky behaviour)
0 Reception is ongoing or is finished
1 No reception activity since last clear
bit 2
RDRF Reception Data Register Full (sticky behaviour)
0 Reception data register is empty
1 Reception data register is full
bit 3
TDRE Transmission Data Register Empty (sticky behaviour)
0 Transmission data register is full
1 Transmission data register is empty
bit 4 to bit 7
- Read value is undefined, always write 0
n = 0...9 according to device ( Please refer to
the datasheet of the corresponding device)
Function