Fujitsu MB96300 series Hardware Manual page 503

MB96300 Super Series Hardware Manual
Table 20.4-7 Function of each bit of the extended serial interrupt register (ESIRn)
Bit name
bit3 TDRE:
Transmission Data
Register Empty
(sticky behaviour)
bit2 RDRF:
Reception Data
Register Full (sticky
behaviour)
bit1 RBI:
Reception Bus Idle
(sticky behaviour)
bit0 AICD:
Auto Interrupt Clear
Disable
• This flag has the same function as SSR:TDRE but it is not cleared when data is
written to the transmission data register TDR.
• This flag indicates the status of the transmission data register (TDR).
• This bit is set to 1 when data is loaded into the transmission shift register and
transmission starts.
• This bit must be cleared by writing "0".
• When AICD = "0" and SSR:TIE = "1", then SSR:TDRE is used to generate a
transmit interrupt.
• When AICD = "1" and SSR:TIE = "1", then ESIR:TDRE is used to generate a
transmit interrupt.
Note:
This bit is set to 1 (TDR empty) as its initial value.
• This flag has the same function as SSR:RDRF but it is not cleared when data is read
from the reception data register RDR.
• This flag indicates the status of the reception data register (RDR).
• This bit is set to 1 when reception data is loaded into RDR.
• This bit must be cleared by writing "0".
• When AICD = "0" and SSR:RIE = "1", then SSR:RDRF is used to generate a receive
interrupt.
• When AICD = "1" and SSR:RIE = "1", then ESIR:RDRF is used to generate a
receive interrupt.
• This flag has the same function as ECCR:RBI but it is not cleared when the reception
bus is no longer idle.
• When there is no reception activity ongoing, this bit is set to "1".
• It must be cleared by writing "0".
• When AICD = "0" and ECCR:BIE = "1", then ECCR:RBI is used to generate a
receive interrupt.
• When AICD = "1" and ECCR:BIE = "1", then ESIR:RBI is used to generate a
receive interrupt.
Note:
When an interrupt shall be generated by a bus idle condition, set AICD = "1". When
AICD = "0", ECCR:RBI would be used for interrupt generation. As soon as the bus
is no longer idle, ECCR:RBI is "0" and the interrupt may be removed even before
the interrupt handling routine could acknowledge it.
• When this bit is "0", then SSR:TDRE, SSR:RDRF and ECCR:RBI are used to
generate interrupts. In this mode, the USART can not be used together with DMA.
• When this bit is "1", then ESIR:TDRE, ESIR:RDRF and ESIR:RBI are used to
generate interrupts. In this mode, the USART can be used together with DMA.
Note:
When AICD = "0", the USART can not be used with DMA. If DMA is used to
handle data transfers of the USART, set AICD = "1".
CHAPTER 20 USART
Function
495