Fujitsu MB96300 series Hardware Manual page 382

F2mc-16fx 16-bit
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CHAPTER 14 16-BIT I/O TIMER
■ Clearing the counter at Compare Clear Register value match
Figure 14.3-6 Clearing the Counter when the Compare Clear Register Value matches the 16-bit Free-
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Compare
register value
Interrupt
■ 16-bit Free-Running Timer timing
16-bit Free-Running Timer clear timing (match with the compare register 0)
The counter can be cleared upon a reset, software clear, or a match with the compare register 0. By a reset,
the counter is immediately cleared. By a match with compare register 0 or Compare Clear Register value or
by software clear (TCCS:CLR = 1), the counter is cleared in synchronization with the count timing.
Figure 14.3-7 16-bit Free-Running Timer clear timing (match with the compare register 0)
φ
Compare
register value
Compare match
Counter value
374
Running Timer value
BFFF
H
N
N
MB96300 Super Series Hardware Manual
Time
0000

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