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MB96300 Super Series Hardware Manual
3.6
Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user.
■ Hardware interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations:
• comparison between the interrupt request level (IL) and the value in the interrupt level mask register
(ILM) of PS in the CPU, and
• hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
• The S flag is set.
•
Sets ILM in the PS register. The currently requested interrupt level (IL) is automatically set.
•
Fetches the corresponding interrupt vector and branches to the processing indicated by that value.
If the device is in standby mode, a hardware interrupt with IL<7 generates a wake-up event to the clock and
mode control unit.
■ Structure of the hardware interrupt system
The interrupt status is indicated by internal resources, the ICR for the interrupt controller, and the PS value of
the CPU. To use a hardware interrupt, make the following set-up:
• Interrupt vector (in memory)
- Consider the TBR value for a non-default location of the vector table.
- The start address of the interrupt service routine has to be written to the appropriate interrupt vector
(VecAddr = 4*(255-INT#) + 256*TBR).
• Peripheral resource
- Use the Interrupt enable and request bits to control interrupt requests from peripheral resources.
• Interrupt controller
- Assign interrupt levels (ICR:IL) for each interrupt, which can occur.
- If interrupts occur simultaneously, a higher priority is defined by lower interrupt levels. IL=7 disables
the interrupt.
- If multiple requests are at the same level, the interrupt controller selects the request with the lowest
interrupt number. In the case of same levels configured, the delayed interrupt has the lowest priority,
independent from its interrupt number.
- There is a fixed relationship between the interrupt requests and the ILs. A level can be defined by IL[n]
for each hardware interrupt request IRQ[n] (for n >= 12).
• CPU
- ILM and I in the PS register are used to compare the requested interrupt level (IL) with the current
interrupt level mask (ILM) and to identify the interrupt enable status (I). For acceptance of hardware
CHAPTER 3 INTERRUPTS
101
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