Fujitsu MB96300 series Hardware Manual page 509

MB96300 Super Series Hardware Manual
20.5.2 Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the transmission data is transferred from
transmission data register (TDRn) to transmission shift register and started.
■ Transmission interrupt generation and flag set timing
A transmission interrupt is generated, when the next data to be sent is ready to be written to the Transmission
Data Register (TDRn), i. e. the TDRn is empty, and the transmission interrupt is enabled by setting the
Transmission Interrupt Enable (TIE) bit of the Serial Status Register (SSRn) to "1".
The Transmission Data Register Empty (TDRE) flag bit of the SSRn indicates an empty TDRn. Writing data
to TDRn clears the TDRE bit.
The following figure demonstrates the transmission operation and flag set timing for the four modes of
USART.
Mode 0, 1 or 3:
write to TDR
TDRE
serial output
Mode 2 (SSM = 0):
write to TDR
TDRE
serial output
ST: Start bit
Note:
The example in Figure 20.5-3 "Transmission operation and flag set timing" does not show all possible
transmission options for mode 0. Here it is: "8p1" (p = "E" [even] or "O" [odd]). Parity is not provided in
mode 3 or 2, if SSM = 0.
Figure 20.5-3 Transmission operation and flag set timing
transmission interrupt occurs
ST D0 D1 D2 D3 D4 D5 D6 D7
transmission interrupt occurs
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
D0 ... D7: data bits P: Parity
transmission interrupt occurs
P
SP ST D0 D1 D2 D3 D4 D5 D6 D7
AD
transmission interrupt occurs
SP: Stop bit AD: Address/data selection bit (mode1)
CHAPTER 20 USART
P
SP
AD
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