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Figure 34.2-3 ROM timing configuration register 1 (MFMTC1)
Address:
0003F3
H
15
14
13
ATD-
EQL2 EQL1
EQL0
EQD1
R/W R/W R/W R/W R/W
Bit name
bit 8 -
-
bit 15
12
11
10
9
8
ATD-
ATD-
ATDL1 ATDL0
EQD0
INIT
R/W R/W R/W
bit8
ATDINIT
bit10
ATDL1
bit12
ATDEQD1
bit15
bit14
EQL2
EQL1
0
0
0
0
1
1
1
1
•
Only available for compatibility with Flash interface but without func-
tionallity. Any values can be writen here.
CHAPTER 34 MASK-ROM MEMORY INTERFACE
Initial value
0 0 0 0 0 0 1 0
B
Flash compatibility
0
ATDIN parked in '0' position
1
ATDIN parked in '1' position
bit9
ATDL0
Flash compatibility
0
0
ATDIN falling edge at access start
0
1
ATDIN falling edge delayed by 0.5 CLKS1 cycles
1
0
ATDIN falling edge delayed by 1.0 CLKS1 cycles
1
1
ATDIN falling edge delayed by 1.5 CLKS1 cycles
bit11
Flash compatibility
ATDEQD0
0
0
EQIN posedge 0.5 CLKS1 cycles after ATDIN negedge
0
1
EQIN posedge 1.0 CLKS1 cycles after ATDIN negedge
1
0
EQIN posedge 1.5 CLKS1 cycles after ATDIN negedge
1
1
EQIN posedge 2.0 CLKS1 cycles after ATDIN negedge
bit13
EQL0
Flash compatibility
0
0
EQIN length is 0.5 CLKS1 cycles
0
1
EQIN length is 1.0 CLKS1 cycles
1
0
EQIN length is 1.5 CLKS1 cycles
1
1
EQIN length is 2.0 CLKS1 cycles
0
0
EQIN length is 2.5 CLKS1 cycles
0
1
EQIN length is 3.0 CLKS1 cycles
1
0
EQIN length is 3.5 CLKS1 cycles
1
1
EQIN length is 4.0 CLKS1 cycles
Function
895
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