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Figure 6.2-4 Configuration of the Clock Stabilization Select Register (CKSSR)
7
6
Address:
000402
SRFBE MRFBE PCST SCST1 SCST0
H
R/W R/W R/W R/W R/W
R/W
: Readable and writable
: Initial value
5
4
3
2
1
0
MCST2 MCST1 MCST0
R/W R/W R/W
Initial value
1 1 1 1 1 1 1 1
B
bit2
bit1
bit0
Main Clock Stabilization Time
(The corresponding time for a Main
MCST2
MCST1
MCST0
clock of 4MHz is given in parentheses)
10
0
0
0
2
/ CLKMC (approx. 256µs)
12
0
0
1
2
/ CLKMC (approx. 1ms)
13
0
1
0
2
/ CLKMC (approx. 2ms)
14
0
1
1
2
/ CLKMC (approx. 4ms)
15
1
0
0
2
/ CLKMC (approx. 8ms)
16
1
0
1
2
/ CLKMC (approx. 16ms)
17
1
1
0
2
/ CLKMC (approx. 32ms)
18
1
1
1
2
/ CLKMC (approx. 65ms)
bit4
bit3
Sub Clock Stabilization Time
(The corresponding time for a Sub
SCST1
SCST0
clock of 32.768kHz is given in parentheses)
12
0
0
2
/ CLKSC (125ms)
14
0
1
2
/ CLKSC (0.5s)
15
1
0
2
/ CLKSC (1s)
16
1
1
2
/ CLKSC (2s)
bit5
PLL Clock Stabilization Time
(The corresponding time for a Main
PCST
clock of 4MHz is given in parentheses)
12
0
2
/ CLKMC (approx. 1ms)
14
1
2
/ CLKMC (approx. 4ms)
bit6
MRFBE
Main oscillator Resistor Feedback Enable
0
Feedback resistor disabled
1
Feedback resistor enabled
bit7
SRFBE
Sub oscillator Resistor Feedback Enable
0
Feedback resistor disabled
1
Feedback resistor enabled
CHAPTER 6 CLOCKS
157
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