Fujitsu MB96300 series Hardware Manual page 171

6.2.5 PLL and clock frequency Control Register (PLLCR)
The PLL and clock frequency Control Register (PLLCR) is used to control all functions
of the PLL multiplier circuit and to control the Peripheral Clock Divider of CLKP3.
■ Configuration of the PLL and clock domain 3 frequency Control Register (PLLCR)
Figure 6.2-6 show the configuration of the PLL and clock domain frequency 3 Control Registers (PLLCR)
and Table 6.2-5 describes the function of each bit.
The register can be accessed 16-bit wide (PLLCR) and 8-bit wide (low byte: PLLCRL, high byte
PLLCRH).
CHAPTER 6 CLOCKS
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