Underflow Operation Of 16-Bit Reload Timer - Fujitsu MB96300 series Hardware Manual

MB96300 Super Series Hardware Manual
15.4

Underflow Operation of 16-bit Reload Timer

An underflow is defined for this timer as the time when the counter value changes from
0000 to FFFF . Therefore, an underflow occurs after (reload register setting + 1) counts.
H H
■ Underflow operation of 16-bit Reload Timer
If the RELD bit in the control status register is "1" and an underflow occurs, the contents of the reload
register is loaded into the counter and counting continues.
If the RELD bit in the control status register is "0", counting stops when counter reaches FFFF
The UF bit in the control status register is set when the underflow occurs. If the INTE bit is "1" at this time,
an interrupt request is generated.
Figure 15.4-1 "Underflow operation of 16-bit reload timer" shows the operation when an underflow occurs.
Counter clock
Counter
UF flag
Counter clock
Counter
UF flag
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT
Figure 15.4-1 Underflow operation of 16-bit reload timer
0000 Reload data
H
0000
H
-1
[RELD = 1]
FFFF
H
[RELD = 0]
.
H
-1 -1
405