Fujitsu MB96300 series Hardware Manual page 551

F2mc-16fx 16-bit

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Table of Contents

Figure 21.1-1 Block diagram

Clock Divider 1

2 3 4 5 ... 32

Clock Selector

Clock Divider 2 (by 12)

SCL Duty Cycle Generator

Repeated start

Send/receive

Arbitration Loss Detector

Start-Stop Condition

ACK Generator

GC-ACK enable

General call

enable 7 bit mode

enable 10 bit mode

received ad. length

Bus Observer

Address Data

Interrupt Request

Slave Address

CHAPTER 21 400 kHz I

Shift Clock Generator