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CHAPTER 30 USB Mini-host
30.5.7
SOF Interrupt
This chapter describes the SOF interrupt processing.
■ SOF Interrupt
Once the HCNT0:SOFIRE bit is set, setting then HIRQ:SOFIRQ bit to "1" will trigger an interrupt
when a SOF starts according to HCNT1:SOFSTEP and the SOF interrupt FRAME comparison
register (HFCOMP) settings. A SOF interrupt can be generated either every time a SOF is sent
out by setting the HCNT1:SOFSTEP bit or periodically by setting the Frame number in the lower
8 bits indicated by the SOF interrupt FRAME comparison register (HFCOMP).
The SOF execution with the host token endpoint register (HTOKEN) does not set automatically
the HIRQ:SOFIRQ bit to "1".
For " 0 " the SOFSTEP bit of host control register 1(HCNT1)
SOFIRQ bit of HIRQ
For " 0 " the SOFSTEP bit of host control register 1(HCNT1)
HFRAME
HFCOMP
SOFIRQ bit of HIRQ
If a token other than SOF (in the HTOKEN) is set in the EOF area, and the HIRQ:SOFIRQ bit is set
to "1" in the next SOF while HCNT1:CANCEL bit is set, the token is not executed and the
HTOKEN:TKNEN bits are set to 000
Cancellation of a token can be known by checking the HIRQ:TCAN (Token Cancellation) flag
after the IRQ:SOFIRQ flag is raised. If the token is executed again, HIRQ:TCAN flag must be
cleared, and the token settings must be specified again in the HTOKEN:TKNEN field.
If the HCNT1:CANCEL bit is reset, the token set in the HTOKEN register is executed after the
SOF is sent.
804
Figure 30.5-6 SOF Interrupt
The SOF
transmission
Soft clear
The SOF
transmission
(010
)
H
(011
. In this case, the HIRQ:CMPIRQ bit is not raised.
B
following SOF
transmission
Soft clear
following SOF
transmission
(011
)
H
)
H
HFRAME lower 8 bit and
HFCOMP is corresponding.
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