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CHAPTER 24 REAL TIME CLOCK
24.2.2
Sub-Second Register
The Sub-Second Register stores a reload value for the 21-bit counter that divides the
oscillation clock. The reload value is usually set so that the 21-bit counter will output
exactly within a half second cycle. This register is not initialized by reset, but 21-bit
counter is initialized by reset.
■ Sub-Second Register (WTBR)
Sub-second register
15
D15
R/W
Initial value:
X
R/W : Readable and writable
-
: Undefined
Application Notes:
The Sub-Second Registers, WTBR, holds values to be reloaded to the 21 bit down counter. When the 21 bit
down counter value becomes "0", the settings of WTBR are reloaded to the 21 bit down counter.
Remark: The reload value to be set in the sub-second registers corresponds to the time for half a second. One
second is reached after counting twice the reload value set in WTBR.
Table 24.2-1 Example configuration of WTBR registers for different clock
configurations
648
Figure 24.2-5 Sub-Second Register (WTBR)
WTBRH0
14
13
12
11
10
9
D14
D13
D12
D11
D10
D9
R/W R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
Main oscillator, 4MHz
RC oscillator, 2MHz
RC oscillator, 100kHz
Sub oscillator, 32.768kHz
MB96300 Super Series Hardware Manual
WTBRL0
8
7
6
5
4
3
D8
D7
D6
D5
D4
D3
R/W
R/W
R/W R/W
R/W
R/W
X
X
X
X
X
X
7
6
5
4
3
-
-
D20
D19
-
-
-
R/W
R/W
-
-
-
X
X
WTBR1
WTBRH0
0F
42
H
07
A1
H
00
61
H
00
20
H
2
1
0
WTBR0
D2
D1
D0
R/W
R/W
R/W
X
X
X
2
1
0
WTBR1
D18
D17
D18
R/W
R/W
R/W
X
X
X
WTBRL0
40
H
H
20
H
H
A8
H
H
00
H
H
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