Fujitsu MB96300 series Hardware Manual page 174

CHAPTER 6 CLOCKS
Table 6.2-5 Function Description of Each Bit of the PLL Control Register (PLLCR) (2/2)
Bit name
bit 8- PC3D0 to PC3D3:
bit 11 Peripheral Clock 3
Division select bits
bit 12 - Reserved
bit 15
166
For devices that do support CLKP3
• These bits control the clock divider for the Peripheral clock (CLKP3) according to
the following table:
bit11 bit10 bit9
PC3D3 PC3D2 PC3D1
0 0 0
0 0 0
0 0 1
... ... ...
1 1 1
1 1 1
• These bits are initialized to "0000" (CLKP3 = CLKS2) by each reset
For devices that do not support CLKP3
These bits are reserved.
• Always write "0" to these bits.
• The read value of these bits is undefined.
• Read modify write operations to this register are not affected.
• Always write "0" to these bits.
• The read value of these bits is undefined.
• Read modify write operations to this register are not affected.
Function
bit8
PC3D0 Peripheral Clock 3 Division select bits
0 CLKP3 is CLKS2 (divided by 1)
1 CLKP3 is CLKS2 divided by 2
0 CLKP3 is CLKS2 divided by 3
... CLKP3 is CLKS2 divided by PC3D[3:0]
0 CLKP3 is CLKS2 divided by 15
1 CLKP3 is CLKS2 divided by 16
+ 1
B