Fujitsu MB96300 series Hardware Manual page 925

F2mc-16fx 16-bit

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Table of Contents

MB96300 Super Series Hardware Manual

Table A-1 I/O map of MB96V300 (7/50)

PPG5 - Duty cycle register

PPG5 - Duty cycle register

PPG5 - Control status register

PPG5 - Control status register

I2C0 - Bus Status Register

I2C0 - Bus Control Register

I2C0 - Ten bit Slave address Register Low

I2C0 - Ten bit Slave address Register High

I2C0 - Ten bit Address mask Register Low

I2C0 - Ten bit Address mask Register High

I2C0 - Seven bit Slave address Register

I2C0 - Seven bit Address mask Register

I2C0 - Data Register

I2C0 - Clock Control Register

I2C1 - Bus Status Register

I2C1 - Bus Control Register

I2C1 - Ten bit Slave address Register Low

I2C1 - Ten bit Slave address Register High

I2C1 - Ten bit Address mask Register Low

I2C1 - Ten bit Address mask Register High

I2C1 - Seven bit Slave address Register

I2C1 - Seven bit Address mask Register

I2C1 - Data Register

I2C1 - Clock Control Register

USART0 USART - Serial Mode Register

USART0 - Serial Control Register

USART0 - TX Register

USART0 - RX Register

USART0 - Serial Status

USART0 - Control/Com. Register

APPENDIX A I/O Map of MB96V300

Abbreviation

8-bit access

16-bit access