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CHAPTER 21 400 kHz I
Seven bit slave address MasK register (ISMKn)
Data Register (IDARn)
Clock control register (ICCRn)
R/
W
:
Readable and writable
-
:
Undefined
546
2
C INTERFACE
15
ENSB
R/W R/W R/W R/W
7
D7 D6 D5 D4 D3 D2
R/W R/W R/W R/W
15
-
14
13
12
11
10
SM6 SM5 SM4 SM3 SM2 SM1SM0
R/W
R/W
R/W R/W
6
5
4
3
2
R/W
R/W
R/W R/W
14
13
12
11
10
NSF EN CS4 CS3 CS2 CS1 CS0
-
R/W R/W R/W
R/W
R/W
R/W R/W
9
8
ISMKn
Initial value
0 1 1 1 1 1 1 1
1
0
IDARn
D1 D0
Initial value
0 0 0 0 0 0 0 0
9
8
ICCRn
Initial value
0 0 0 1 1 1 1 1
B
B
B
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