Reset, System Clock And Stabilization Wait Times - Fujitsu MB96300 series Hardware Manual

MB96300 Super Series Hardware Manual
8.2

Reset, System clock and Stabilization Wait Times

The F2MC-16FX family has five reset causes. The System clocks (CLKS1 and CLKS2) are
set to RC clock after each reset. The stabilization wait time depends on the reset cause
and the status of the RC oscillator when the reset occurs.
■ Reset causes and stabilization wait times
Table 8.2-1 summarizes which stabilization times are applied for the different reset causes.
Table 8.2-1 Reset cause and stabilization wait times
Reset cause
Power reset
External reset
Clock stop
detection reset
Software reset
Watchdog
timer reset
Each reset activates the RC oscillator, Main oscillator and Sub oscillator, stops the PLL and resets the Clock
Stabilization Select Register (CKSSR).
A Power or External reset clears all clock ready monitor bits.
Other types of resets only clear the PLL and RC clock ready monitor bit, but not the Main and Sub clock
ready monitor bits. Active clocks stay active and disabled clocks are activated and become ready after the
stabilization time defined in the CKSSR register.
See CHAPTER 6 "CLOCKS", for more details about selected clocks and oscillation stabilization wait times.
■ Stabilization wait time in case of an External reset
The stabilization wait time in case of an External reset consists of two parts, the External reset extension time
and the RC clock stabilization time. The External reset extension time starts counting with the assertion of
RST (falling edge) while the RC clock stabilization time starts counting after RST release. Hence the start of
the program execution depends on the assertion time of RST as follows:
●
External reset asserted for more than 700 RC clock cycles
The External reset extension time is already expired in this case. Hence the CPU starts executing the Boot
ROM program after the RC clock stabilization time of 64 RC clock cycles after clearing the External reset.
700 + 64 = 764 RC clock cycles (approximately 380µs at 2MHz nominal RC clock
frequency). This wait time starts AFTER reaching a valid power supply (external
and internal voltage). The 700 RC clock cycles are the Power reset extension time
and the 64 cycles are the RC clock stabilization time.
700 + 64 = 764 RC clock cycles (approximately 380µs at 2MHz nominal RC clock
frequency). The 700 RC clock cycles are the External reset extension time which
starts already at the falling edge of the RST input signal while the 64 cycles are the
RC clock stabilization time which is applied after RST release.
RC clock stabilization time of 64 RC clock cycles is applied.
CHAPTER 8 RESETS AND STARTUP
Stabilization wait time
195