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CHAPTER 10 SOURCE CLOCK TIMERS
Figure 10.3-2 Configuration of the Main Clock Timer Control Register (MCTCR)
15
Address:
000409
-
MCTIE MCTIF MCTR MCTI3
H
-
R/W R/W
X
: undefined value
W
: Write only (read always returns "1")
R/W
: Readable and writable
: Initial value
270
14
13
12
11
10
9
8
MCTI2 MCTI1 MCTI0
W
R/W
R/W R/W R/W
bit11
MCTI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MB96300 Super Series Hardware Manual
Initial value
X 0 0 1 0 0 0 0
B
bit10
bit9
bit8
Main Clock Timer Interrupt interval
(The corresponding time for a Main
MCTI2
MCTI1
MCTI0
clock of 4MHz is given in parentheses)
8
0
0
0
2
/ CLKMC (approx. 64µs)
9
0
0
1
2
/ CLKMC (approx. 128µs)
10
0
1
0
2
/ CLKMC (approx. 256µs)
11
0
1
1
2
/ CLKMC (approx. 512µs)
12
1
0
0
2
/ CLKMC (approx. 1ms)
13
1
0
1
2
/ CLKMC (approx. 2ms)
14
1
1
0
2
/ CLKMC (approx. 4ms)
15
1
1
1
2
/ CLKMC (approx. 8ms)
16
0
0
0
2
/ CLKMC (approx. 16ms)
17
0
0
1
2
/ CLKMC (approx. 32ms)
18
0
1
0
2
/ CLKMC (approx. 65ms)
19
0
1
1
2
/ CLKMC (approx. 131ms)
20
1
0
0
2
/ CLKMC (approx. 262ms)
21
1
0
1
2
/ CLKMC (approx. 524ms)
22
1
1
0
2
/ CLKMC (approx. 1.049s)
23
1
1
1
2
/ CLKMC (approx. 2.097s)
bit12
Main Clock Timer Reset bit
MCTR
Read
0
always reads 1
1
bit13
Main Clock Timer Interrupt Flag
MCTIF
Read
0
no interrupt
1
interrupt requested
bit14
MCTIE
Main Clock Timer Interrupt Enable bit
0
Disable Interrupt
1
Enable Interrupt
bit15
-
Reserved
0
Always write "0" to this bit
Write
reset all bits to 0
no effect
Write
clear this bit
no effect
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