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CHAPTER 29 USB FUNCTION
The function of each bit in the EP1 to EP5 status register (EP1S to EP5S) is described in the following.
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
750
Bit names
BIFNI
• This bit initializes the transmission/reception buffer.
• The BFINI bit is automatically set when the RST flag in the
• When the reset operation has been performed with the RST bit,
• The transmission/receive buffer for EP1 to EP5 has a
• Buffer must be initialized after having set the STAL bit. To do
DRQIE
• DRQ interrupt enable. It enables an interrupt to be triggered
• In automatic buffer transfer mode (DMAE = "1"), DMA settings
SPKIE
• This bit enables an interrupt to be triggered by the SPK flag of
Undefined
• No functionnality.
BUSY
• This bit indicates that writing into the transmission/receive
• It is set/reset automatically.
• BUSY indicates that the HOST is accessing a buffer that is
• If the buffer is being initialized by setting BFINI, the buffer must
DRQ
• This bit indicates that EPn packet has been successfully
•
• Writing "1" is ignored.
• Clear by writing "0". "1" is read at the read modification write.
• After the data write of the transmission buffer is processed, the
• When DRQ = "0", writing "0" is prohibited.
• When the automatic buffer transfer mode (DMAE=1) is not used
UDC control register (UDCC) is set to 0.
clear the RST bit before clearing the BFINI bit.
configuration of double buffers. Initialization by BFINI bit
initializes the double buffers, the DRQ and SPK bits all at once.
so, DRQ bit must be set and the BUSY bit must show that no
access from the HOST is being performed.
when the DRQ flag of one of the EP1S to EP5S is set.
must be enabled before setting DRQIE.
each EP1S to EP5S register.
buffer or accessing it for read from the HOST is in progress.
different from either the double buffer accessed by the CPU or
the DMA when DRQ and the BUSY flag are set.
be initialized by setting the STAL bit after DRQ is set and no
access from the HOST is in progress.
transferred and data processing is needed.
The DRQ bit trigger an interrupt.
DRQ must be cleared.
after the data read or write of transmission and reception buffers
is processed, "0" must be write to DRQ bit. When DRQ bit is
cleared, access buffer is switched. When the transfer direction is
set to IN direction if DRQ bit is "1" and the buffer is cleared
without writing data, 0-byte data is set to it. In the initial setting,
when the DIR of the EP1 to EP5 control register (EP1C to
EP5C) is set to "1", DRQ bit of the corresponding end point is
set at the same time. Furthermore, writing 0 is prohibited when
DRQ bit is not set
Function
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