Fujitsu MB96300 series Hardware Manual page 398

F2mc-16fx 16-bit
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CHAPTER 14 16-BIT I/O TIMER
■ Input Capture Control Status Register (ICS(2n)(2n+1))
Figure 14.5-3 Input Capture Control Status Register (ICS(2n)(2n+1))
R/W R/W R/W R/W R/W
R/W
:
:
Remark:
The suffix "n" denotes the Input Capture Unit number (0, 1, 2, ...). The register name and the bit names are
composed by the register/bit type name and the suffix. For example:
• for Input Capture Unit 0: n = 0, hence ICS01 has bits EG01, EG00, EG11, EG10, ICE0, ICE1, ICP0, ICP1
• for Input Capture Unit 1: n = 1, hence ICS23 has bits EG21, EG20, EG21, EG20, ICE2, ICE3, ICP2, ICP3
• etc.
390
7
6
5
4
3
2
ICE ICE EG
EG
ICP
ICP
EG
R/W
R/W R/W
Readable and writable
Initial value
MB96300 Super Series Hardware Manual
1
0
initial value
0 0 0 0 0 0 0 0
EG
.
.
bit1
bit0
EG(2n)1
EG(2n)0
Edge selection bit (Input Capture 2n)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
bit3
bit2
EG(2n+1)1 EG(2n+1)0 Edge selection bit (Input Capture (2n+1))
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
bit4
Interrupt Enable Bit (Input Capture 2n)
ICE(2n)
0
Disable Interrupt
1
Enable Interrupt
bit5
Interrupt Enable Bit (Input Capture (2n+1))
ICE(2n+1)
0
Disable Interrupt
1
Enable Interrupt
bit6
Interrupt request flag bit
ICP(2n)
Read
0
No edge detected
1
Edge detected
bit7
Interrupt request flag bit
ICP(2n+1)
Read
0
No edge detected
1
Edge detected
ICS(2n)(2n+1)
B
(Input Capture 2n)
Write
Clear this bit
No effect
(Input Capture (2n+1))
i
Write
Clear this bit
No effect
n = 0, 1, 2, ...

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