Fujitsu MB96300 series Hardware Manual page 855

F2mc-16fx 16-bit
Hide thumbs Also See for MB96300 series:
Table of Contents

Advertisement

Table 33.4-1 Function of each bit of the Flash Memory Control Status register (MFMCS/SFMCS)
Bit names
bit 0
RDY:
Flash RDY
status
bit 1
RDYINT:
RDY Interrupt
flag
bit 2
INTE:
Interrupt
Enable bit
bit 3
WE:
Write Enable
bit
bit 4
CRBE:
Code Read
Buffer Enable
bit
bit 5
DRBE:
Data Read
Buffer Enable
bit
This bit shows the status of the (sampled) Flash RDY output.
Writing to this bit has no effect.
A read value of '0' indicates that a program/erase command is currently executed.
Only the reset and suspend commands are accepted in this state.
A read value of '1' indicates that no program/erase command is currently
executed. Any command can be written to the Flash.
This bit is the interrupt flag of the Flash ready interrupt function.
This bit is initialized to '0' by reset.
It is set to '1' by a rising edge of the RDY signal.
The RDYINT bit can be cleared by writing to '0'. Writing to '1' has no effect.
The read cycle of a read-modify-write access always returns '1'.
This bit permits the CPU to generate an interrupt when a write/erase command
terminates.
An interrupt is generated when this bit is set to '1' and the RDYINT flag gets set
by a rising edge of the RDY signal.
When this bit is set to '0', no interrupts can be generated.
The initial value of the INTE bit is '0'.
This bit is read- and writable.
This bit enables/disables writing to the Flash.
WEX is forced to '1' when this bit is '0'. Hence no write/erase commands can be
sent to the Flash.
Setting this bit to '1' enables WEX and command writing.
The initial value of this bit is '0'.
This bit enables/disables the code read buffer.
Setting this bit to '1' enables the code read buffer. A code read access from any
address reads two 16-bit words, the one that is addressed and the neighbouring
one, such that the resulting two 16-bit words are aligned to an even address. Both
words are stored into a read buffer. A later CPU read access to the address of the
buffered data will be executed without wait cycles.
Setting this bit to '0' disables the code read buffer. Code is always read directly
from the Flash.
The initial value of this bit is '1' (buffer enabled).
This bit enables/disables the data read buffer.
Setting this bit to '1' enables the data read buffer. A data read access from any
address reads two 16-bit words, the one that is addressed and the neighbouring
one, such that the resulting two 16-bit words are aligned to an even address. Both
words are stored into a read buffer. A later CPU read access to the address of the
buffered data will be executed without wait cycles.
Setting this bit to '0' disables the data read buffer. Data is always read directly
from the Flash.
The initial value of this bit is '1' (buffer enabled).
CHAPTER 33 FLASH MEMORY
Function
847

Advertisement

Table of Contents
loading

Table of Contents