Fujitsu F2MC-16LX Series Manuals

Manuals and User Guides for Fujitsu F2MC-16LX Series. We have 5 Fujitsu F2MC-16LX Series manuals available for free PDF download: Hardware Manual, User Manual, Application Note

Fujitsu F2MC-16LX Series Hardware Manual (706 pages)

16-bit Microcontroller MB90330 series

Brand: Fujitsu | Category: Microcontrollers | Size: 13.48 MB

Table Of Contents 9

CHAPTER 1 OVERVIEW 17

Feature Of MB90330 Series 18

Block Diagram 23

Package Dimension 24

Pin Assignment 26

Pin Function 27

I/O Circuit Types 34

Handling Of Device 37

CHAPTER 2 CPU 41

Outline Specification Of CPU 42

Memory Space 43

Accumulator (A) 50

User Stack Pointer (USP) And System Stack Pointer (SSP) 51

Processor Status (PS) 52

Program Counter (PC) 55

Program Bank Register (PCB) 56

Direct Page Register (DPR) 57

General-purpose Registers (Register Bank) 58

Prefix Code 59

CHAPTER 3 INTERRUPT 63

Outline Of Interrupt 64

Interrupt Cause And Interrupt Vector 67

Interrupt Control Register And Peripheral Function 70

Interrupt Control Registers (ICR00 To ICR15) 72

Interrupt Control Register Functions 74

Hardware Interrupt 77

Operation Of Hardware Interrupt 80

Operation Flow Of Hardware Interrupt 82

Procedure For Using A Hardware Interrupt 83

Multiple Interrupts 84

Hardware Interrupt Processing Time 86

Software Interrupt 88

Interrupts By Extended Intelligent I/O Service (EI 2 OS) 90

Extended Intelligent I/O Service 92

OS) Descriptor (ISD) 92

Each Register Of Extended Intelligent I/O Service 94

Operation Of Extended Intelligent I/O Service (EI 2 OS) 97

Procedure For Use Of Extended Intelligent I/O Service (EI 2 OS) 98

OS) Processing Time 99

Exception Processing Interrupt 102

Interruption By µDMAC 103

µDMAC Function 104

DMA Descriptor Channel Specification Register (DCSR) 106

DMA Status Register (DSRH/DSRL) 108

DMA Stop Status Register (DSSR) 109

DMA Permission Register (DERH/DERL) 110

DMA Descriptor Window Register (DDWR) 111

DMA Data Counter (DDCTH/DDCTL) 112

DMA I/O Register Address Pointer (DIOAH/DIOAL) 113

DMA Control Register (DMACS) 114

DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) 116

Explanation Of Operation Of µDMAC 117

Exceptions 119

Stack Operation Of Interrupt Processing 120

Program Example Of Interrupt Processing 122

Delayed Interrupt Generation Module 126

Operation Of Delayed Interrupt Generation Module 127

CHAPTER 4 RESET 129

Outline Of Reset 130

Reset Factors And Oscillation Stabilization Wait Times 132

External Reset Pin 134

Reset Operation 135

Reset Factor Bit 137

State Of Each Pin At Reset 139

CHAPTER 5 CLOCK 141

Outline Of Clock 142

Block Diagram Of Clock Generation Section 145

Clock Select Register (CKSCR) 148

Clock Mode 151

Oscillation Stabilization Wait Time 154

Connection Of Oscillator And External Clock 155

CHAPTER 6 LOW-POWER CONSUMPTION MODE 157

Outline Of Low-Power Consumption Mode 158

Block Diagram Of Low-power Consumption Control Circuit 161

Low-power Consumption Mode Control Register (LPMCR) 163

CPU Intermittent Operation Mode 166

Standby Mode 167

Sleep Mode 168

Timebase Timer Mode 170

Watch Mode 172

Stop Mode 174

State Transition Diagram 176

State Of The Pin During Standby Mode, Hold, And Reset 178

Precautions When Using Low-power Consumption Mode 188

CHAPTER 7 MODE SETTING 191

Mode Setting 192

Mode Pins (MD2 To MD0) 193

Mode Data 194

External Memory Access 198

Automatic Ready Function Selection Register (ARSR) 200

External Address Output Control Register (HACR) 201

Bus Control Signal Selection Register (EPCR) 202

Operation In Each Mode Of Mode Setting 204

External Memory Access Control Signal 205

Ready Function 208

Holding Function 211

CHAPTER 8 I/O PORT 213

Functions Of I/O Ports 214

I/O Port Register 215

Port Data Register (PDR0 To PDRB) 216

Port Direction Register (DDR0 To DDRB) 217

Other Registers 218

CHAPTER 9 TIMEBASE TIMER 221

Overview Of Timebase Timer 222

Configuration Of Timebase Timer 224

Timebase Timer Control Register (TBTC) 226

Interrupt Of Timebase Timer 228

Operations Of Timebase Timer 229

Precautions When Using Timebase Timer 231

Program Example Of Timebase Timer 233

CHAPTER 10 WATCHDOG TIMER 235

Overview Of Watchdog Timer 236

Watchdog Timer Control Register (WDTC) 238

Configuration Of Watchdog Timer 240

Operations Of Watchdog Timer 242

Precautions When Using Watchdog Timer 244

Program Examples Of Watchdog Timer 245

CHAPTER 11 WATCH TIMER 247

Overview Of Watch Timer 248

Configuration Of Watch Timer 249

Watch Timer Control Register (WTC) 250

Operation Of Watch Timer 252

CHAPTER 12 16-BIT I/O TIMER 254

Overview Of 16-bit I/O Timer 254

16-bit Free-run Timer 257

Output Compare 263

Input Capture 268

Operation Of 16-bit I/O Timer 271

Operation Of 16-bit Free-run Timer 272

Operation Of 16-bit Output Compare 274

Operation Of 16-bit Input Capture 276

Timing Of 16-bit Free-run Timer 277

Output Compare Timing 278

Input Timing Of Input Capture 279

CHAPTER 13 USB FUNCTION 281

Overview Of USB Function 282

Block Diagram Of USB Function 283

UDC Control Register (UDCC) 287

EP0 Control Register (EP0C) 290

EP1 To EP5 Control Register (EP1C To EP5C) 292

Time Stamp Register (TMSP) 295

UDC Status Register (UDCS) 296

UDC Interruption Enable Register (UDCIE) 300

EP0I Status Register (EP0IS) 302

EP0O Status Register (EP0OS) 304

EP1 To EP5 Status Register (EP1S To EP5S) 307

EP0 To EP5 Data Register (EP0DT To EP5DT) 311

Operation Explanation Of USB Function 312

Each Register Operation When Command Responds 316

Suspend Function 318

Wake-up Function 319

DMA Transfer Function 320

NULL Transfer Function 324

CHAPTER 14 USB Mini-HOST 325

Feature Of USB Mini-HOST 326

Diversity With USB HOST 327

Block Diagram Of USB Mini-HOST 328

Host Control Register 0,1(HCNT0/HCNT1) 332

Host Interruption Register (HIRQ) 336

Host Error Status Register (HERR) 339

Host State Status Register (HSTATE) 342

SOF Interruption FRAME Comparison Register (HFCOMP) 345

Retry Timer Setting Register (HRTIMER) 346

Host Address Register (HADR) 347

EOF Setting Register (HEOF) 348

FRAME Setting Register (HFRAME) 349

Host Token Endpoint Register (HTOKEN) 350

Operation Of USB Mini-HOST 352

Connection Of Device 353

Reset Of USB Bus 355

Token Packet 356

Data Packet 358

Handshake Packet 359

Retry Function 360

SOF Interrupt 361

Error Status 363

Packet End 364

Suspend Resume 365

Cutting Of Device 368

Each Token Flow Chart Of USB Mini-HOST 369

CHAPTER 15 PWC TIMER 371

Overview Of PWC Timer 372

PWC Control Status Register (PWCSR) 375

PWC Data Buffer Register (PWCR) 380

PWC Ratio Of Dividing Frequency Control Register (DIVR) 381

Movement Of PWC Timer 382

Operation Of PWM Timer Functions 383

Operation Of Pulse Width Measurement Function 384

Count Clock Selection And Operation Mode Selection 385

Startup And Stop Of Timer/Pulse Width Measurement 387

Operation Of Timer Mode 389

Operation Of Pulse Width Measurement Mode 392

Precautions When Using PWC Timer 397

CHAPTER 16 16-BIT RELOAD TIMER 399

Overview Of 16-bit Reload Timer 400

Function Of 16-bit Reload Timer 401

Block Diagram Of 16-bit Reload Timer 403

Registers Of 16-bit Reload Timer 404

Timer Control Status Register 0 To 2 (TMCSR0 To TMCSR2) 405

16-bit Timer Register 0 To 2 (TMR0 To TMR2)/ 16-bit Reload Register 0 To 2 (TMRLR0 To TMRLR2) 409

Movement Of 16-bit Reload Timer 411

State Transition Of Counter Operation 412

Operation Of Internal Clock Mode (Reload Mode) 413

Operation Of Internal Clock Mode (Single Shot Mode) 415

Event Count Mode 417

CHAPTER 17 8/16-BIT PPG TIMER 419

Overview Of 8/16-bit PPG Timer 420

Block Diagram Of 8/16-bit PPG Timer 421

Registers Of 8/16-bit PPG Timer 423

PPG0/PPG2/PPG4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) 424

PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) 426

PPG0 To PPG5 Output Control Register (PPG01/PPG23/PPG45) 429

PPG Reload Registers (PRLL0 To PRLL5, PRLH0 To PRLH5) 431

Operation Of 8/16-bit PPG Timer 432

CHAPTER 18 DTP/EXTERNAL INTERRUPT 437

Overview Of DTP/External Interrupt 438

Operation Of DTP/External Interrupt 441

Precaution Of Using DTP/External Interrupt 443

CHAPTER 19 8/10-BIT A/D CONVERTER 446

Overview Of 8/10-bit A/D Converter 446

Configuration Of 8/10-bit A/D Converter 447

A/D Control Status Register (High) (ADCS1) 450

A/D Control Status Register (Low) (ADCS0) 452

A/D Conversion Channel Set Register (ADMR) 454

A/D Data Register (ADCR1/ADCR0) 456

Explanation Of Operation Of 8/10-bit A/D Converter 458

Conversion Operation Using µDMAC Or EI 461

A/D-converted Data Protection Function 462

Precautions When Using 8/10-bit A/D Converter 464

Example Of Program-1 Of 8/10-bit A/D Converter (Example Of Starting The EI 2 OS In The Single Mode) 465

Example Of Program-2 Of 8/10-bit A/D Converter (Example Of Starting The EI 2 OS In The Continuous Mode) 468

Example Of Program-3 Of 8/10-bit A/D Converter (Example Of Starting The EI 2 OS In The Stop Mode) 471

CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 475

Outline Of Extended I/O Serial Interface 476

Serial Mode Control Status Register (SMCS) 478

Serial Data Register (SDR) 482

Communication Prescaler Control Register (SDCR) 483

Operation Of Extended I/O Serial Interface 484

Shift Clock Mode 485

Operation State Of Serial I/O 486

Start/stop Timing Of Shift Operation And Timing Of I/O 488

Interrupt Function 490

CHAPTER 21 UART 491

Overview Of UART 492

UART Block Diagram 494

UART Pins 497

Serial Control Register 0 To 3 (SCR0 To SCR3) 499

Serial Mode Register 0 To 3 (SMR0 To SMR3) 501

Serial Status Register 0 To 3 (SSR0 To SSR3) 503

Serial Input Data Register 0 To 3(SIDR0 To SIDR3) And Serial Output Data Register0 To 3(SODR0 To SODR3) 506

UART Prescaler Control Register 0 To 3 (UTCR0 To UTCR3) And UART Prescaler Reload Register 0 To 3 (UTRLR0 To UTRLR3) 508

UART Interrupt 510

Receive Interrupt Generation And Flag Set Timing 512

Transmit Interrupt Generation And Flag Set Timing 514

UART Baud Rate 516

Baud Rate Of The UART Internal Clock Using The Dedicated Baud Rate Generator 517

Baud Rate Of The External Clock Using The Dedicated Baud Rate Generator 518

Baud Rate Of The External Clock (One-to-one Mode) 519

Explanation Of Operation Of UART 520

Operation In Asynchronous Mode (Operation Mode 0 Or Operation Mode1) 522

Operation In Synchronous Mode (Operation Mode 2) 525

Bidirectional Communication Function (Normal Mode) 528

Master/Slave Mode Communication Function (Multi-processor Mode) 530

Notes On Using UART 533

Example Of UART Programming 534

CHAPTER 22 I 2 C INTERFACE 537

I 2 C Interface Outline 538

I 2 C Interface Register 540

I 2 C Bus Status Register 0 To 2 (IBSR0 To IBSR2) 541

I 2 C Bus Control Register 0 To 2 (IBCR0 To IBCR2) 543

I 2 C Bus Clock Control Register 0 To 2 (ICCR0 To ICCR2) 548

I 2 C Bus Address Register 0 To 2 (IADR0 To IADR2) 550

I 2 C Bus Data Register 0 To 2 (IDAR0 To IDAR2) 551

I 2 C Interface Operation 552

Transfer Flow Of I C Interface 554

Mode Flow Of I 556

Interface 556

Operation Flow Of I C Interface 557

CHAPTER 23 ROM MIRROR FUNCTION SELECTION MODULE 559

Overview Of ROM Mirror Function Select Module 560

ROM Mirror Function Select Register (ROMM) 561

CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 563

Overview Of Address Match Detection Function 564

Block Diagram Of Address Match Detection Function 565

Configuration Of Address Match Detection Function 566

Address Detection Control Register (PACSR) 567

Detect Address Setting Registers (PADR0, PADR1) 569

Explanation Of Operation Of Address Match Detection Function 571

Example Of Using Address Match Detection Function 572

Program Example Of Address Match Detection Function 577

CHAPTER 25 3M-BIT FLASH MEMORY 579

Overview Of 3M-bit Flash Memory 580

Sector Configuration Of 3M-bit Flash Memory 581

Flash Memory Control Status Register (FMCS) 582

Automatic Algorithm Initiation Method Of Flash Memory 585

Check The Execution State Of Automatic Algorithm 586

Data Polling Flag (DQ7) 588

Toggle Bit Flag (DQ6) 589

Timing Limit Over Flag (DQ5) 590

Sector Erasing Timer Flag (DQ3) 591

Toggle Bit 2 Flag (DQ2) 592

Write/Erase Of Flash Memory 593

Read/Reset State In Flash Memory 594

Writing Data To Flash Memory 595

Erasing All Data From Flash Memory (Chip Erase) 597

Erasing Any Data In Flash Memory (Sector Erasing) 598

Flash Memory Sector Erase Suspension 600

Flash Memory Sector Erase Resumption 601

CHAPTER 26 EXAMPLE Of CONNECTING SERIAL WRITING 603

Basic Configuration 604

Oscillation Clock Frequency And Serial Clock Input Frequency 606

Flash Microcomputer Programmer System Configuration 607

Example Of Connecting Serial Writing 608

Example Connection In Single-chip Mode (when Using User Power) 609

Example Of Minimum Connection To Flash Microcomputer Programmer (when Using User Power) 611

APPENDIX 613

Appendix A Memory Map 614

Appendix B Instruction 630

Instruction Types 631

B.1 Instruction Types 631

Addressing 632

B.2 Addressing 632

Direct Addressing 634

B.3 Direct Addressing 634

Indirect Addressing 639

B.4 Indirect Addressing 639

Execution Cycle Count 645

Effective Address Field 648

How To Read The Instruction List 649

F 2 MC-16LX Instruction List 651

Instruction Map 665

B.9 Instruction Map 665

Fujitsu F2MC-16LX Series Hardware Manual (598 pages)

MB90470 Series 16-BIT MICROCONTROLLER

Brand: Fujitsu | Category: Microcontrollers | Size: 16.23 MB

Table Of Contents 9

CHAPTER 1 OVERVIEW OF MB90470 17

Overview 18

Block Diagram Of MB90470 21

Package Dimensions 22

Pin Assignment 24

Pin Functions 26

I/O Circuit Type 32

Handling The Device 35

CHAPTER 2 CPU 37

Overview Of CPU Specifications 38

Memory Space 39

CPU Registers 43

Accumulator (A) 45

User Stack Pointer (USP) And System Stack Pointer (SSP) 46

Processor Status (PS) 47

Program Counter (PC) 50

Program Count Bank Register (PCB) 51

Direct Page Register (DPR) 52

General-Purpose Register (Register Bank) 53

Prefix Codes 54

CHAPTER 3 INTERRUPT 57

Overview 58

Interrupt Factor And Interrupt Vector 60

Interrupt Control Register And Peripheral Function 63

Interrupt Control Register (ICR00 To ICR15) 65

Interrupt Control Register Functions 68

Hardware Interrupt 71

Hardware Interrupt Operation 74

Flow Of Hardware Interrupt Operation 76

Procedure For Using Hardwar Interrupt 77

Multiple Interrupts 79

Hardware Interrupt Processing Time 81

Software Interrupt 83

Interrupt By µDMA 85

DMA Descriptor 89

Individual Registers Of DMA Descriptor 91

DMA Processing Procedure 94

µDMA Processing Time 95

Interrupt Of Extended Intelligent I/O Service (EI 2 OS) 97

Extended Intelligent I/O Service 99

OS) Descriptor (ISD) 99

Description Of Extended Intelligent I/O Service (EI 2 OS) Descriptor (ISD) 101

Operation Of Extended Intelligent I/O Service (EI 2 OS) 104

Setting Procedure Of Extended Intelligent I/O Service (EI 2 OS) 105

Processing Time For Extended Intelligent I/O Service (EI 2 OS) 106

Exception Processing Interrupt By Executing Undefined Instruction 109

Stack Operation Of Interrupt Processing 110

Sample Program Of Interrupt Processing 112

Delay Interrupt Event Module 115

Operation Of Delay Interrupt Event Module 116

CHAPTER 4 RESET 117

Overview Of Reset 118

Reset Factors And Oscillation Stabilization Wait Time 120

External-Reset Pin 122

Resetting 123

Reset-Factor Bits 125

Condition Of Pins As Result Of Reset 127

CHAPTER 5 CLOCKS 129

Overview 130

Block Diagram Of Clock Generator 132

Clock Selection Register (CKSCR) 134

Clock Modes 137

Oscillation Stabilization Wait Time 141

Connecting Oscillator To External Clock 142

CHAPTER 6 LOW-POWER CONSUMPTION MODE 143

Overview Of Low-Power Consumption Mode 144

Block Diagram Of Low-power Control Circuit 147

Low-Power Consumption Mode Control Register (LPMCR) 149

CPU Intermittent Operation Mode 152

Standby Mode 153

Sleep Mode 154

Timebase Timer Mode 156

Watch Mode 158

Stop Mode 160

State Transition Diagram 162

Pin State In Standby Mode, Hold, And Reset 164

Caution On Using Low-Power Consumption Mode 169

CHAPTER 7 MODE SETTING 173

Mode Setting 174

Mode Pins (MD2 To MD0) 175

Mode Data 176

External Memory Access 180

Automatic Ready Function Selection Register (ARSR) 182

External Address Output Control Register (HACR) 184

Bus Control Signal Selection Register (EPCR) 185

Operation Of Each Mode For Mode Setting 187

External Memory Access Control Signals 188

Ready Function 191

Hold Function 194

CHAPTER 8 I/O PORT 197

Functions Of I/O Port 198

Registers For I/O Port 199

Port Registers (PDR0 To PDRA) 200

Port Direction Registers (DRR0 To DRRA) 201

Other Registers 203

CHAPTER 9 TIMEBASE TIMER 205

Overview 206

Timebase Timer Configuration 208

Timebase Timer Control Register (TBTC) 210

Timebase Timer Interrupt 212

Timebase Timer Operation 213

Notes On Using Timebase Timer 215

Sample Programs 217

CHAPTER 10 WATCHDOG TIMER 219

Overview 220

Watchdog Timer Control Register (WDTC) 222

Watchdog Timer Configuration 224

Watchdog Timer Operation 226

Notes On Using Watchdog Timer 228

Sample Programs 229

CHAPTER 11 WATCH TIMER 231

Overview 232

Watch Timer Configuration 233

Watch Timer Control Register (WTC) 234

Watch Timer Operation 236

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 239

16-bit Input/Output Timer Register 242

16-bit Free-running Timer 243

Output Compare 248

Input Capture 252

16-bit Input/Output Timer Operation 255

Operation Of 16-bit Free-running Timer 256

Operation Of 16-bit Output Compare 258

Operation Of 16-bit Input Capture 260

16-bit Free-running Timer Timing 261

Output Compare Timing 262

Timing Of Input Capture 263

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 265

Overview 266

Registers For 8/16-bit Up/Down Counter/Timer 269

Counter Control Register H0 (CCRH0) 270

Counter Control Register H1 (CCRH1) 272

Counter Control Register L0/1 (CCRL0/1) 274

Counter Status Register 0/1 (CSR0/1) 276

Up/down Count Register 0/1 (UDCR0/1) 278

Reload/compare Register 0/1 (RCR0/1) 279

8/16-bit Up/Down Counter/Timer Operation 280

Reload/compare Function 283

Writing Data To Up/down Count Register (UDCR) 286

CHAPTER 14 PWC TIMER 289

Overview Of PWC Timer 290

PWC Timer Registers 292

PWC Control/Status Register (PWCSR0 To PWCSR2) 293

PWC Data Buffer Register (PWCR0 To PWCR2) 298

Divide Ratio Control Register (DIVR0 To DIVR2) 299

Operations Of PWC Timer 300

Operations Of The Timer Function 301

Operations Of The Pulse Width Measurement Function 302

Selection Of Count Clock And Operation Mode 304

Start And Stop Of Timer/Pulse Width Measurement 306

Timer Mode Operation 308

Operation In Pulse Width Measurement Mode 311

Notes On PWC Timer Usage 317

CHAPTER 15 µ µ µ µ PG TIMER 319

Overview Of µPG Timer 320

µPG Timer Registers 321

Timing Chart Of µPG Timer 323

CHAPTER 16 16-BIT RELOAD TIMER 325

Overview Of 16-Bit Reload Timer 326

Functions Of The 16-Bit Reload Timer 327

Block Diagram Of The 16-Bit Reload Timer 329

16-Bit Reload Timer Registers 330

Timer Control Status Register (TMCSR) 331

16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) 335

Operations Of The 16-Bit Reload Timer 337

State Transitions During Counter Operation 338

Operations Of Internal Clock Mode (Reload Mode) 339

Internal Clock Mode (One-Shot Mode) 341

Event Count Mode 343

CHAPTER 17 8/16-BIT PPG TIMER 345

Overview Of 8/16-bit PPG Timer 346

Block Diagram Of The 8/16-Bit PPG Timer 347

8/16-bit PPG Timer Registers 349

PPG0/2/4 Operation Mode Control Register (PPGC0) 350

PPG1/3/5 Operation Mode Control Register (PPGC1) 352

PPG0 To PPG5 Output Control Registers (PPG0/1, PPG2/3, PPG4/5) 355

Reload Registers (PPLL0 To PPLL5, PPLH0 To PPLH5) 357

Operations Of 8/16-Bit PPG Timer 358

CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 363

Overview Of DTP/External Interrupt Unit 364

DTP/External Interrupt Unit Registers 365

Operations Of DTP/External Interrupt Unit 367

Notes On DTP/External Interrupt Unit Usage 369

CHAPTER 19 8/10-BIT A/D CONVERTER 371

Overview Of 8/10-bit A/D Converter 372

8/10-bit A/D Converter Registers 374

Control Status Register 1 (ADCS1) 375

Control Status Register 2 (ADCS2) 378

Data Registers (ADCR2 And ADCR1) 381

Operations Of 8/10-bit A/D Converter 382

Example Of µDMA Start In Single Mode 384

Example Of µDMA Start In Continuous Mode 386

Example Of µDMA Start In Stop Mode 388

Conversion Data Protection Function 390

Precautions When Using The 8/10-bit A/D Converter 392

CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 393

Overview Of Expanded I/O Serial Interface 394

Registers Of Expanded I/O Serial Interface 395

Serial Mode Control Status Register (SMCS) 396

Serial Shift Data Register (SDR) 400

Dedicated Prescaler Control Register (SDCR) 401

Operation Of Expanded I/O Serial Interface 402

Shift Clock Modes 403

Operational States Of Serial I/O Units 404

Start/Stop Timing And Input/Output Timing Of Shift Operation 406

Interrupt Function 408

CHAPTER 21 UART 409

Overview Of The UART 410

UART Registers 412

Serial Mode Register (SMR) 413

Serial Control Register (SCR) 415

Serial Input/Output Register (SIDR/SODR) 417

Serial Status Register (SSR) 418

Communication Prescaler Control Register (CDCR) 420

UART Operations 422

Operation In Asynchronous Mode (Operation Modes 0 And 1) 426

Operation In Synchronous Mode (Operation Mode 2) 429

Two-Way Communication Function (Normal Mode) 431

Master/Slave Communication Function (Multiprocessor Mode) 433

Precautions On Using The UART 436

UART Program Example 437

CHAPTER 22 I 2 C INTERFACE 439

Overview Of I C Interface 440

I 2 C Interface Registers 442

Bus Status Register (IBSR) 443

Bus Control Register (IBCR) 445

Clock Control Register (ICCR) 448

Address Register (IADR) 450

Data Register (IDAR) 451

I 2 C Interface Operation 452

CHAPTER 23 CHIP SELECTION FACILITY 455

Overview Of Chip Selection Facility 456

Registers Of Chip Selection Facility 457

Chip Select Area MASK Register (CMRx) 458

Chip Selection Area Register (CARx) 459

Chip Selection Control Register (CSCR) 460

Chip Selector Active Level Register (CALR) 461

Operation Of The Chip Selection Facility 462

CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 465

Overview Of Address Match Detection Function 466

Block Diagram Of Address Match Detection Function 467

Configuration Of Address Match Detection Function 468

Address Detection Control Register (PACSR) 469

Detect Address Setting Registers (PADR0H And PADR1) 471

Explanation Of Operation Of Address Match Detection Function 473

Example Of Using Address Match Detection Function 474

Program Example Of Address Match Detection Function 479

CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE 481

Overview Of ROM Mirror Function Select Module 482

ROM Mirror Function Select Register (ROMM) 483

CHAPTER 26 2M BIT FLASH MEMORY 485

Overview Of 2M Bit Flash Memory 486

Sector Configuration Of 2M Bit Flash Memory 487

Control Status Register (FMCS) 488

Method For Starting The Flash Memory's Automatic Algorithm 491

Verifying The Execution State Of The Automatic Algorithm 492

Data Polling Flag (DQ7) 494

Toggle Bit Flag (DQ6) 496

Timing Limit Excess Flag (DQ5) 497

Sector Erase Timer Flag (DQ3) 498

Flash Memory Write/Erase Operations 499

Setting The Flash Memory To Read/Reset State 500

Writing Data To Flash Memory 501

Erasing All Data In The Flash Memory (Chip Erase) 503

Erasing Arbitrary Data In Flash Memory (Sector Erase) 504

Suspending Sector Erasure For The Flash Memory 506

Resuming The Sector Erasure Of Flash Memory 507

CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 509

Basic Configuration 510

Oscillation Clock Frequency And Serial Clock Input Frequency 512

System Configuration Of Flash Microcomputer Programmer 513

Examples Of Serial Programming Connection 514

Example Of Connection In Single-Chip Mode (Using Power From User System) 515

Example Of Minimum Connection With Flash Microcomputer Programmer (Using Power From The User System) 517

APPENDIX 519

APPENDIX A Memory Map 520

APPENDIX B Instructions 531

Instruction Types 532

B.1 Instruction Types 532

Addressing 533

B.2 Addressing 533

Direct Addressing 535

B.3 Direct Addressing 535

Indirect Addressing 540

B.4 Indirect Addressing 540

Execution Cycle Count 546

Effective Address Field 549

How To Read The Instruction List 550

F 2 MC-16LX Instruction List 553

Instruction Map 567

B.9 Instruction Map 567

INDEX 589

Fujitsu F2MC-16LX Series Hardware Manual (486 pages)

MB90550A/B Series, 16-BIT

Brand: Fujitsu | Category: Microcontrollers | Size: 7.3 MB

Table Of Contents 9

CHAPTER 1 OVERVIEW 17

Features 18

Available Models 21

Block Diagram 22

External Dimensions Of The Package 23

Pin Assignment 25

Description Of The Pin Functions 27

I/O Circuit Types 33

Cautions On Handling Devices 37

CHAPTER 2 CPU 41

Memory Space 42

Addressing 43

Allocating Multiple-byte Data In A Memory Space 46

Dedicated Registers 47

Accumulator (A) 49

User Stack Pointer (USP) And System Stack Pointer (SSP) 51

Processor Status (PS) 52

Program Counter (PC) 55

Direct Page Register (DPR) 56

Bank Registers (PCB, DTB, USB, SSB, ADB) 57

General-purpose Registers 58

Prefix Codes 60

Interrupt Suppression Instructions And Prefix Codes 62

Notes On Using The "DIV A, Ri" And "DIVW A, RWi" Instructions 63

CHAPTER 3 INTERRUPTS 67

Overview Of Interrupts 68

Interrupt Causes 69

Interrupt Vectors 72

Hardware Interrupts 74

Operation Of Hardware Interrupts 77

Operating Flow For Hardware Interrupts 80

Example Of Procedure For Using Hardware Interrupts 81

Software Interrupts 82

Expanded Intelligent I/O Service (EI 2 OS) 84

Interrupt Control Register (ICR) 86

Expanded Intelligent I/O Service Descriptor (ISD) 89

Operation Of The Expanded Intelligent I/O Service (EI 2 OS) 93

Execution Time Of The Expanded Intelligent I/O Service (EI 2 OS) 95

Exceptions Because Of Executing Undefined Instructions 96

CHAPTER 4 GENERATING AND RESETTING CLOCKS 97

Clock Generator 98

Clock Supply Map 99

Reset Causes 100

Operation After A Reset Is Released 102

Registers Not Initialized By Reset Input 103

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 105

Overview Of The Low-power Consumption Control Circuit 106

Low-power Consumption Mode Control Register (LPMCR) 109

Clock Selection Register (CKSCR) 111

Operation Of The Low-power Consumption Control Circuit 114

Sleep Mode 116

Watch Mode 117

Stop Mode 119

Hardware Standby Mode 120

Pin Status In The Sleep, Stop, Hold, Reset, And Hardware Standby Modes 121

Intermittent CPU Operation Function 124

Setting The Oscillation Stabilization Time 125

Machine Clock 126

CHAPTER 6 MEMORY ACCESS MODES 129

Memory Access Mode Overview 130

Mode Pins 131

Mode Data 132

Memory Space For Each Bus Mode 133

External Memory Access (External Bus Pin Control Circuit) 136

Registers For External Memory Access (External Bus Pin Control Circuit) 137

Automatic Ready Function Selection Register (ARSR) 138

External Address Output Control Register (HACR) 140

Bus Control Signal Selection Register (ECSR) 141

Operation Of The External Memory Access Control Signals 144

Ready Function 146

Hold Function 148

CHAPTER 7 I/O PORTS 149

I/O Port Overview 150

I/O Port Block Diagram 151

I/O Port Registers 154

Port Data Registers (PDRx) 156

Port Data Direction Registers (DDRx) 158

Output Pin Register (ODR4) 159

Input Resistor Registers (RDR0 And RDR1) 160

Analog Input Enable Register (ADER) 161

CHAPTER 8 TIME-BASED TIMER 163

Overview Of The Time-Based Timer 164

Time-Based Timer Control Register (TBTC) 165

Time-Based Timer Operations 167

CHAPTER 9 WATCHDOG TIMER 169

Overview Of The Watchdog Timer 170

Watchdog Timer Control Register (WDTC) 171

Watchdog Timer Operations 173

CHAPTER 10 16-BIT I/O TIMER 175

Overview Of The 16-Bit I/O Timer 176

16-Bit I/O Timer Block Diagram 178

16-Bit I/O Timer Registers 179

16-bit Free-run Timer 181

Output Compare 184

Input Capture 188

16-Bit Free-Run Timer Operations 190

16-Bit Output Compare Operations 192

16-Bit Input Capture Operations 195

Overview Of The 16-Bit Reload Timer (with The Event Count Function) 198

Registers Of The 16-Bit Reload Timer (with The Event Count Function) 199

Timer Control Status Register (TMCSR) 200

16-Bit Timer Register (TMR) And 16-Bit Reload Register (TMRLR) 203

Clock Operations 204

Underflow Operation 205

I/O Pin Functions 206

Counter Operation Statuses 208

CHAPTER 12 8/16-BIT PPG 209

Overview Of The 8/16-Bit PPG 210

Block Diagrams Of The 8-Bit PPG 211

Registers In The 8/16-Bit PPG 213

PPG0 Operation Mode Control Register (PPGC0) 214

PPG1 Operation Mode Control Register (PPGC1) 216

PPG0/1 Output Pin Control Register (PPGE) 219

Reload Registers (PRLL/PRLH) 221

8/16-Bit PPG Operation 222

8/16-bit PPG Operation Modes 224

PPG Output Operation 225

Selecting A Count Clock 227

Controlling Pulse Output On Pins 228

Write Timing For The Reload Registers 229

CHAPTER 13 DTP/EXTERNAL INTERRUPT 231

Overview Of The DTP/External Interrupt Circuit 232

Registers In The DTP/External Interrupt Circuit 234

Operation Of DTP/External Interrupt Circuit 237

Notes On Using The DTP/External Interrupt Circuit 240

CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE 243

Outline Of The Delayed Interrupt Generating Module 244

Operation Of The Delayed Interrupt Generating Module 245

CHAPTER 15 A/D CONVERTER 247

Overview Of The A/D Converter 248

Resisters Of The A/D Converter 251

Control Status Registers (ADCS0 And ADCS1) 252

Data Register (ADCR1 And ADCR0) 256

Operation Of A/D Converter 258

Example Of EI OS Activation In Single Mode 260

Example Of EI OS Activation In Successive Mode 262

Example Of EI 2 OS Activation In Successive Mode 262

Example Of EI OS Activation In Pause Mode 264

Example Of EI 2 OS Activation In Pause Mode 264

Conversion Data Protection Function 266

CHAPTER 16 COMMUNICATION PRESCALER REGISTER 269

Overview Of Communication Prescaler Register 270

Operation Of Communication Prescaler Register 272

CHAPTER 17 UART 273

Overview Of UART 274

UART Block Diagram 275

UART Registers 276

Serial Mode Register (SMR) 277

Serial Control Register (SCR) 279

Serial Input Data Register (SIDR) And Serial Output Data Register (SODR) 282

Serial Status Register (SSR) 283

UART Operations 286

UART Clock Selection 287

Asynchronous (Start-stop Synchronous) Mode 289

CLK-synchronous Mode 291

Occurrence Of Interrupt And Flag Setting Timing 293

Application Of UART (During Operation In Mode 1) 296

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE 299

Overview Of The I/O Extended Serial Interface 300

Registers Of The I/O Extended Serial Interface 302

Serial Mode Control Status Register (SMCS) 303

Serial Shift Data Register (SDR) 307

Operation Of I/O Extended Serial Interface 308

Shift Clock 309

Operation States Of The Serial I/O 311

Start/Stop Timing Of Shift Operation And Input/Output Timing 313

Interrupt Function Of The I/O Extended Serial Interface 316

CHAPTER 19 I 2 C INTERFACE 318

C Interface 318

Block Diagram And Structure Of The I 319

Registers Of The I C Interface 321

Bus Status Register (IBSR) 322

Bus Control Register (IBCR) 325

Clock Control Register (ICCR) 328

Address Register (IADR) 330

Data Register (IDAR) 331

Port Selection Register (ISEL) 332

Operation Of The I C Interface 333

Flow Of The I 2 C Interface Transmission 335

Flow Of The I C Interface Modes 337

CHAPTER 20 CLOCK MONITOR FUNCTION 339

Overview Of The Clock Monitor Functions 340

Clock Output Permission Register (CLKR) 341

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 343

Overview Of The Address Match Detection Function 344

Registers Of The Address Match Detection Function 345

Operation Of The Address Match Detection Function 347

Example Of The Address Match Detection Function 348

Program Example Of The Address Match Detection Function 350

CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE 353

Overview Of The ROM Mirror Function Selection Module 354

ROM Mirror Function Selection Register (ROMM) 355

CHAPTER 23 1M-BIT FLASH MEMORY 357

Overview Of The 1M-Bit Flash Memory 358

Block Diagram And Sector Configuration Of The Entire Flash Memory 359

Writing And Deletion Modes 361

Flash Memory Control Status Register (FMCS) 363

Activating The Automatic Algorithm Of The Flash Memory 365

Confirming The Automatic Algorithm Execution Status 366

Data Polling Flag (DQ7) 368

Toggle Bit Flag (DQ6) 370

Timing Limit Excess Flag (DQ5) 371

Sector Deletion Timer Flag (DQ3) 372

Detailed Explanations Of Flash Memory Writing And Deletion 373

Setting The Flash Memory In The Read Or Reset Status 374

Writing Data In The Flash Memory 375

Deleting All Data Items From The Flash Memory (Chip Deletion) 377

Deleting Any Data Item From The Flash Memory (Sector Deletion) 378

Temporarily Stopping The Sector Deletion From The Flash Memory 380

Restarting The Flash Memory Sector Deletion 381

Example Of The 1M-Bit Flash Memory Program 382

CHAPTER 24 EXAMPLE OF MB90F553A SERIAL PROGRAMMING CONNECTION 387

Basic Configuration Of MB90F553A Serial Programming Connection 388

Example Of Serial Programming Connection (When User Power Supply Is Used) 391

Example Of Serial Programming Connection (When Power Is Supplied From A Writer) 393

(When User Power Supply Is Used) 395

Example Of Minimal Connection With The Flash Microcontroller Programmer (When Power Is Supplied From A Writer) 397

APPENDIX 399

APPENDIX A I/O MAP 400

APPENDIX B Instructions 408

Instruction Types 409

B.1 Instruction Types 409

Addressing 410

B.2 Addressing 410

Direct Addressing 412

B.3 Direct Addressing 412

Indirect Addressing 418

B.4 Indirect Addressing 418

Execution Cycle Count 426

Effective Address Field 429

How To Read The Instruction List 430

F 2 MC-16LX Instruction List 433

Instruction Map 447

B.9 Instruction Map 447

APPENDIX C Programming The OTPROM 469

INDEX 471

Fujitsu F2MC-16LX Series User Manual (14 pages)

PC Serial Programming Adapter Cable for Fujitsu Flash Microcontroller-F²MC-16LX/FR Family

Brand: Fujitsu | Category: Computer Hardware | Size: 0.15 MB

Fujitsu F2MC-16LX Series Application Note (13 pages)

Brand: Fujitsu | Category: Microcontrollers | Size: 0.95 MB

Table Of Contents 3

Introduction 4

Rules To Create A Good Layout 4

Crystal Oscillator Circuit 5

Power Supply Routing 6

Noise Reduction For General IO Pins 9

Function Of Certain MCU Pins 10

EMI Measurement For LX16-family 11

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