Fujitsu F2MC-16LX Series Manuals

• 9

  Table of Contents

17

Chapter 1 Overview

• 18

  Feature of MB90330 Series
• 23

  Block Diagram
• 24

  Package Dimension
• 26

  Pin Assignment
• 27

  Pin Function
• 34

  I/O Circuit Types
• 37

  Handling of Device

41

Chapter 2 Cpu

• 42

  Outline Specification of CPU
• 43

  Memory Space
• 48

  Register of CPU
  • 50

    Accumulator (A)
  • 51

    User Stack Pointer (USP) and System Stack Pointer (SSP)
  • 52

    Processor Status (PS)
  • 55

    Program Counter (PC)
  • 56

    Program Bank Register (PCB)
  • 57

    Direct Page Register (DPR)
  • 58

    General-Purpose Registers (Register Bank)
• 59

  Prefix Code

63

Chapter 3 Interrupt

• 64

  Outline of Interrupt
• 67

  Interrupt Cause and Interrupt Vector
• 70

  Interrupt Control Register and Peripheral Function
  • 72

    Interrupt Control Registers (ICR00 to ICR15)
  • 74

    Interrupt Control Register Functions
• 77

  Hardware Interrupt
  • 80

    Operation of Hardware Interrupt
  • 82

    Operation Flow of Hardware Interrupt
  • 83

    Procedure for Using a Hardware Interrupt
  • 84

    Multiple Interrupts
  • 86

    Hardware Interrupt Processing Time
• 88

  Software Interrupt
• 90

  Interrupts By Extended Intelligent I/O Service (EI 2 OS)
  • 92

    Extended Intelligent I/O Service
• 92

  OS) Descriptor (ISD)
  • 94

    Each Register of Extended Intelligent I/O Service
• 94

  OS) Descriptor (ISD)
  • 97

    Operation of Extended Intelligent I/O Service (EI 2 OS)
  • 98

    Procedure for Use of Extended Intelligent I/O Service (EI 2 OS)
• 99

  OS) Processing Time
  • 102

    Exception Processing Interrupt
  • 103

    Interruption By Μdmac
    • 104

      Μdmac Function
    • 105

      Register of Μdmac
      • 106

        DMA Descriptor Channel Specification Register (DCSR)
      • 108

        DMA Status Register (DSRH/DSRL)
      • 109

        DMA Stop Status Register (DSSR)
      • 110

        DMA Permission Register (DERH/DERL)
    • 111

      DMA Descriptor Window Register (DDWR)
      • 112

        DMA Data Counter (DDCTH/DDCTL)
      • 113

        DMA I/O Register Address Pointer (DIOAH/DIOAL)
      • 114

        DMA Control Register (DMACS)
      • 116

        DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL)
    • 117

      Explanation of Operation of Μdmac
  • 119

    Exceptions
  • 120

    Stack Operation of Interrupt Processing
  • 122

    Program Example of Interrupt Processing
  • 126

    Delayed Interrupt Generation Module
    • 127

      Operation of Delayed Interrupt Generation Module

129

Chapter 4 Reset

• 130

  Outline of Reset
• 132

  Reset Factors and Oscillation Stabilization Wait Times
• 134

  External Reset Pin
• 135

  Reset Operation
• 137

  Reset Factor Bit
• 139

  State of Each Pin at Reset

141

Chapter 5 Clock

• 142

  Outline of Clock
• 145

  Block Diagram of Clock Generation Section
• 148

  Clock Select Register (CKSCR)
• 151

  Clock Mode
• 154

  Oscillation Stabilization Wait Time
• 155

  Connection of Oscillator and External Clock

157

Chapter 6 Low-Power Consumption Mode

• 158

  Outline of Low-Power Consumption Mode
• 161

  Block Diagram of Low-Power Consumption Control Circuit
• 163

  Low-Power Consumption Mode Control Register (LPMCR)
• 166

  CPU Intermittent Operation Mode
• 167

  Standby Mode
  • 168

    Sleep Mode
  • 170

    Timebase Timer Mode
  • 172

    Watch Mode
  • 174

    Stop Mode
• 176

  State Transition Diagram
• 178

  State of the Pin During Standby Mode, Hold, and Reset
• 188

  Precautions When Using Low-Power Consumption Mode

191

Chapter 7 Mode Setting

• 192

  Mode Setting
• 193

  Mode Pins (MD2 to MD0)
• 194

  Mode Data
• 198

  External Memory Access
  • 200

    Automatic Ready Function Selection Register (ARSR)
  • 201

    External Address Output Control Register (HACR)
  • 202

    Bus Control Signal Selection Register (EPCR)
• 204

  Operation in Each Mode of Mode Setting
  • 205

    External Memory Access Control Signal
  • 208

    Ready Function
  • 211

    Holding Function

213

Chapter 8 I/O Port

• 214

  Functions of I/O Ports
• 215

  I/O Port Register
  • 216

    Port Data Register (PDR0 to PDRB)
  • 217

    Port Direction Register (DDR0 to DDRB)
  • 218

    Other Registers

221

Chapter 9 Timebase Timer

• 222

  Overview of Timebase Timer
• 224

  Configuration of Timebase Timer
• 226

  Timebase Timer Control Register (TBTC)
• 228

  Interrupt of Timebase Timer
• 229

  Operations of Timebase Timer
• 231

  Precautions When Using Timebase Timer
• 233

  Program Example of Timebase Timer

235

Chapter 10 Watchdog Timer

• 236

  Overview of Watchdog Timer
• 238

  Watchdog Timer Control Register (WDTC)
• 240

  Configuration of Watchdog Timer
• 242

  Operations of Watchdog Timer
• 244

  Precautions When Using Watchdog Timer
• 245

  Program Examples of Watchdog Timer

247

Chapter 11 Watch Timer

• 248

  Overview of Watch Timer
• 249

  Configuration of Watch Timer
• 250

  Watch Timer Control Register (WTC)
• 252

  Operation of Watch Timer

254

Chapter 12 16-Bit I/O Timer

• 254

  Overview of 16-Bit I/O Timer
• 256

  Register of 16-Bit I/O Timer
  • 257

    16-Bit Free-Run Timer
  • 263

    Output Compare
  • 268

    Input Capture
• 271

  Operation of 16-Bit I/O Timer
  • 272

    Operation of 16-Bit Free-Run Timer
  • 274

    Operation of 16-Bit Output Compare
  • 276

    Operation of 16-Bit Input Capture
  • 277

    Timing of 16-Bit Free-Run Timer
  • 278

    Output Compare Timing
  • 279

    Input Timing of Input Capture

281

Chapter 13 Usb Function

• 282

  Overview of USB Function
• 283

  Block Diagram of USB Function
• 284

  Register of USB Function
  • 287

    UDC Control Register (UDCC)
  • 290

    EP0 Control Register (EP0C)
  • 292

    EP1 to EP5 Control Register (EP1C to EP5C)
  • 295

    Time Stamp Register (TMSP)
  • 296

    UDC Status Register (UDCS)
  • 300

    UDC Interruption Enable Register (UDCIE)
  • 302

    EP0I Status Register (EP0IS)
  • 304

    EP0O Status Register (EP0OS)
  • 307

    EP1 to EP5 Status Register (EP1S to EP5S)
  • 311

    EP0 to EP5 Data Register (EP0DT to EP5DT)
• 312

  Operation Explanation of USB Function
  • 316

    Each Register Operation When Command Responds
  • 318

    Suspend Function
  • 319

    Wake-Up Function
  • 320

    DMA Transfer Function
  • 324

    NULL Transfer Function

325

CHAPTER 14 USB Mini-Host

• 326

  Feature of USB Mini-Host
• 327

  Diversity With USB HOST
• 328

  Block Diagram of USB Mini-Host
• 329

  Register of USB Mini-Host
  • 332

    Host Control Register 0,1(HCNT0/HCNT1)
  • 336

    Host Interruption Register (HIRQ)
  • 339

    Host Error Status Register (HERR)
  • 342

    Host State Status Register (HSTATE)
  • 345

    SOF Interruption FRAME Comparison Register (HFCOMP)
  • 346

    Retry Timer Setting Register (HRTIMER)
  • 347

    Host Address Register (HADR)
  • 348

    EOF Setting Register (HEOF)
  • 349

    FRAME Setting Register (HFRAME)
  • 350

    Host Token Endpoint Register (HTOKEN)
• 352

  Operation of USB Mini-Host
  • 353

    Connection of Device
  • 355

    Reset of USB Bus
  • 356

    Token Packet
  • 358

    Data Packet
  • 359

    Handshake Packet
  • 360

    Retry Function
  • 361

    SOF Interrupt
  • 363

    Error Status
  • 364

    Packet End
  • 365

    Suspend Resume
  • 368

    Cutting of Device
• 369

  Each Token Flow Chart of USB Mini-Host

371

Chapter 15 Pwc Timer

• 372

  Overview of PWC Timer
• 374

  Register of PWC Timer
  • 375

    PWC Control Status Register (PWCSR)
  • 380

    PWC Data Buffer Register (PWCR)
  • 381

    PWC Ratio of Dividing Frequency Control Register (DIVR)
• 382

  Movement of PWC Timer
  • 383

    Operation of PWM Timer Functions
  • 384

    Operation of Pulse Width Measurement Function
  • 385

    Count Clock Selection and Operation Mode Selection
  • 387

    Startup and Stop of Timer/Pulse Width Measurement
  • 389

    Operation of Timer Mode
  • 392

    Operation of Pulse Width Measurement Mode
• 397

  Precautions When Using PWC Timer

399

Chapter 16 16-Bit Reload Timer

• 400

  Overview of 16-Bit Reload Timer
  • 401

    Function of 16-Bit Reload Timer
  • 403

    Block Diagram of 16-Bit Reload Timer
• 404

  Registers of 16-Bit Reload Timer
  • 405

    Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2)
  • 409

    16-Bit Timer Register 0 to 2 (TMR0 to TMR2)/ 16-Bit Reload Register 0 to 2 (TMRLR0 to TMRLR2)
• 411

  Movement of 16-Bit Reload Timer
  • 412

    State Transition of Counter Operation
  • 413

    Operation of Internal Clock Mode (Reload Mode)
  • 415

    Operation of Internal Clock Mode (Single Shot Mode)
  • 417

    Event Count Mode

419

Chapter 17 8/16-Bit Ppg Timer

• 420

  Overview of 8/16-Bit PPG Timer
  • 421

    Block Diagram of 8/16-Bit PPG Timer
• 423

  Registers of 8/16-Bit PPG Timer
  • 424

    PPG0/PPG2/PPG4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4)
  • 426

    PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5)
  • 429

    PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45)
  • 431

    PPG Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5)
• 432

  Operation of 8/16-Bit PPG Timer

437

Chapter 18 Dtp/External Interrupt

• 438

  Overview of Dtp/External Interrupt
• 439

  Register of Dtp/External Interrupt
• 441

  Operation of Dtp/External Interrupt
• 443

  Precaution of Using Dtp/External Interrupt

446

Chapter 19 8/10-Bit A/D Converter

• 446

  Overview of 8/10-Bit A/D Converter
• 447

  Configuration of 8/10-Bit A/D Converter
• 449

  Register of 8/10-Bit A/D Converter
  • 450

    A/D Control Status Register (High) (ADCS1)
  • 452

    A/D Control Status Register (Low) (ADCS0)
  • 454

    A/D Conversion Channel Set Register (ADMR)
  • 456

    A/D Data Register (ADCR1/ADCR0)
• 458

  Explanation of Operation of 8/10-Bit A/D Converter
  • 461

    Conversion Operation Using Μdmac or EI
  • 462

    A/D-Converted Data Protection Function
• 464

  Precautions When Using 8/10-Bit A/D Converter
• 465

  Example of Program-1 of 8/10-Bit A/D Converter (Example of Starting the EI 2 OS in the Single Mode)
• 468

  Example of Program-2 of 8/10-Bit A/D Converter (Example of Starting the EI 2 OS in the Continuous Mode)
• 471

  Example of Program-3 of 8/10-Bit A/D Converter (Example of Starting the EI 2 OS in the Stop Mode)

475

Chapter 20 Extended I/O Serial Interface

• 476

  Outline of Extended I/O Serial Interface
• 477

  Register in Extended I/O Serial Interface
  • 478

    Serial Mode Control Status Register (SMCS)
  • 482

    Serial Data Register (SDR)
  • 483

    Communication Prescaler Control Register (SDCR)
• 484

  Operation of Extended I/O Serial Interface
  • 485

    Shift Clock Mode
  • 486

    Operation State of Serial I/O
  • 488

    Start/Stop Timing of Shift Operation and Timing of I/O
  • 490

    Interrupt Function

491

Chapter 21 Uart

• 492

  Overview of UART
• 494

  UART Block Diagram
• 497

  UART Pins
• 498

  Register of UART
  • 499

    Serial Control Register 0 to 3 (SCR0 to SCR3)
  • 501

    Serial Mode Register 0 to 3 (SMR0 to SMR3)
  • 503

    Serial Status Register 0 to 3 (SSR0 to SSR3)
  • 506

    Serial Input Data Register 0 to 3(SIDR0 to SIDR3) and Serial Output Data Register0 to 3(SODR0 to SODR3)
  • 508

    UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and UART Prescaler Reload Register 0 to 3 (UTRLR0 to UTRLR3)
• 510

  UART Interrupt
  • 512

    Receive Interrupt Generation and Flag Set Timing
  • 514

    Transmit Interrupt Generation and Flag Set Timing
• 516

  UART Baud Rate
  • 517

    Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator
  • 518

    Baud Rate of the External Clock Using the Dedicated Baud Rate Generator
  • 519

    Baud Rate of the External Clock (One-To-One Mode)
• 520

  Explanation of Operation of UART
  • 522

    Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode1)
  • 525

    Operation in Synchronous Mode (Operation Mode 2)
  • 528

    Bidirectional Communication Function (Normal Mode)
  • 530

    Master/Slave Mode Communication Function (Multi-Processor Mode)
• 533

  Notes On Using UART
• 534

  Example of UART Programming

537

Chapter 22 I 2 C Interface

• 538

  I 2 C Interface Outline
• 540

  I 2 C Interface Register
  • 541

    I 2 C Bus Status Register 0 to 2 (IBSR0 to IBSR2)
  • 543

    I 2 C Bus Control Register 0 to 2 (IBCR0 to IBCR2)
  • 548

    I 2 C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2)
  • 550

    I 2 C Bus Address Register 0 to 2 (IADR0 to IADR2)
  • 551

    I 2 C Bus Data Register 0 to 2 (IDAR0 to IDAR2)
• 552

  I 2 C Interface Operation
  • 554

    Transfer Flow of I C Interface
  • 556

    Mode Flow of I
  • 556

    Interface
  • 557

    Operation Flow of I C Interface

559

Chapter 23 Rom Mirror Function Selection Module

• 560

  Overview of ROM Mirror Function Select Module
• 561

  ROM Mirror Function Select Register (ROMM)

563

Chapter 24 Address Match Detection Function

• 564

  Overview of Address Match Detection Function
• 565

  Block Diagram of Address Match Detection Function
• 566

  Configuration of Address Match Detection Function
  • 567

    Address Detection Control Register (PACSR)
  • 569

    Detect Address Setting Registers (PADR0, PADR1)
• 571

  Explanation of Operation of Address Match Detection Function
  • 572

    Example of Using Address Match Detection Function
• 577

  Program Example of Address Match Detection Function

579

Chapter 25 3M-Bit Flash Memory

• 580

  Overview of 3M-Bit Flash Memory
• 581

  Sector Configuration of 3M-Bit Flash Memory
• 582

  Flash Memory Control Status Register (FMCS)
• 585

  Automatic Algorithm Initiation Method of Flash Memory
• 586

  Check the Execution State of Automatic Algorithm
  • 588

    Data Polling Flag (DQ7)
  • 589

    Toggle Bit Flag (DQ6)
  • 590

    Timing Limit Over Flag (DQ5)
  • 591

    Sector Erasing Timer Flag (DQ3)
  • 592

    Toggle Bit 2 Flag (DQ2)
• 593

  Write/Erase of Flash Memory
  • 594

    Read/Reset State in Flash Memory
  • 595

    Writing Data to Flash Memory
  • 597

    Erasing All Data From Flash Memory (Chip Erase)
  • 598

    Erasing Any Data in Flash Memory (Sector Erasing)
  • 600

    Flash Memory Sector Erase Suspension
  • 601

    Flash Memory Sector Erase Resumption

603

CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING

• 604

  Basic Configuration
• 606

  Oscillation Clock Frequency and Serial Clock Input Frequency
• 607

  Flash Microcomputer Programmer System Configuration
• 608

  Example of Connecting Serial Writing
  • 609

    Example Connection in Single-Chip Mode (When Using User Power)
  • 611

    Example of Minimum Connection to Flash Microcomputer Programmer (When Using User Power)

613

Appendix

614

Appendix A Memory Map

630

Appendix B Instruction

• 631

  Instruction Types
• 631

  B.1 Instruction Types
• 632

  Addressing
• 632

  B.2 Addressing
• 634

  Direct Addressing
• 634

  B.3 Direct Addressing
• 639

  Indirect Addressing
• 639

  B.4 Indirect Addressing
• 645

  Execution Cycle Count
• 648

  Effective Address Field
• 649

  How to Read the Instruction List
• 651

  F 2 MC-16LX Instruction List
• 665

  Instruction Map
• 665

  B.9 Instruction Map

• 9

  Table of Contents

17

Chapter 1 Overview

• 18

  Features
• 21

  Available Models
• 22

  Block Diagram
• 23

  External Dimensions of the Package
• 25

  Pin Assignment
• 27

  Description of the Pin Functions
• 33

  I/O Circuit Types
• 37

  Cautions On Handling Devices

41

Chapter 2 Cpu

• 42

  Memory Space
• 43

  Addressing
• 46

  Allocating Multiple-Byte Data in a Memory Space
• 47

  Dedicated Registers
  • 49

    Accumulator (A)
  • 51

    User Stack Pointer (USP) and System Stack Pointer (SSP)
  • 52

    Processor Status (PS)
  • 55

    Program Counter (PC)
  • 56

    Direct Page Register (DPR)
  • 57

    Bank Registers (PCB, DTB, USB, SSB, ADB)
• 58

  General-Purpose Registers
• 60

  Prefix Codes
• 62

  Interrupt Suppression Instructions and Prefix Codes
• 63

  Notes On Using the "DIV A, Ri" and "DIVW A, Rwi" Instructions

67

Chapter 3 Interrupts

• 68

  Overview of Interrupts
• 69

  Interrupt Causes
• 72

  Interrupt Vectors
• 74

  Hardware Interrupts
  • 77

    Operation of Hardware Interrupts
  • 80

    Operating Flow for Hardware Interrupts
  • 81

    Example of Procedure for Using Hardware Interrupts
• 82

  Software Interrupts
• 84

  Expanded Intelligent I/O Service (EI 2 OS)
  • 86

    Interrupt Control Register (ICR)
  • 89

    Expanded Intelligent I/O Service Descriptor (ISD)
  • 93

    Operation of the Expanded Intelligent I/O Service (EI 2 OS)
  • 95

    Execution Time of the Expanded Intelligent I/O Service (EI 2 OS)
• 96

  Exceptions Because of Executing Undefined Instructions

97

Chapter 4 Generating and Resetting Clocks

• 98

  Clock Generator
• 99

  Clock Supply Map
• 100

  Reset Causes
• 102

  Operation After a Reset Is Released
• 103

  Registers Not Initialized By Reset Input

105

Chapter 5 Low-Power Consumption Control Circuit

• 106

  Overview of the Low-Power Consumption Control Circuit
• 109

  Low-Power Consumption Mode Control Register (LPMCR)
• 111

  Clock Selection Register (CKSCR)
• 114

  Operation of the Low-Power Consumption Control Circuit
  • 116

    Sleep Mode
  • 117

    Watch Mode
  • 119

    Stop Mode
  • 120

    Hardware Standby Mode
  • 121

    Pin Status in the Sleep, Stop, Hold, Reset, and Hardware Standby Modes
• 124

  Intermittent CPU Operation Function
• 125

  Setting the Oscillation Stabilization Time
• 126

  Machine Clock

129

Chapter 6 Memory Access Modes

• 130

  Memory Access Mode Overview
  • 131

    Mode Pins
  • 132

    Mode Data
  • 133

    Memory Space for Each Bus Mode
• 136

  External Memory Access (External Bus Pin Control Circuit)
  • 137

    Registers for External Memory Access (External Bus Pin Control Circuit)
  • 138

    Automatic Ready Function Selection Register (ARSR)
  • 140

    External Address Output Control Register (HACR)
  • 141

    Bus Control Signal Selection Register (ECSR)
• 144

  Operation of the External Memory Access Control Signals
  • 146

    Ready Function
  • 148

    Hold Function

149

Chapter 7 I/O Ports

• 150

  I/O Port Overview
• 151

  I/O Port Block Diagram
• 154

  I/O Port Registers
  • 156

    Port Data Registers (Pdrx)
  • 158

    Port Data Direction Registers (Ddrx)
  • 159

    Output Pin Register (ODR4)
  • 160

    Input Resistor Registers (RDR0 and RDR1)
  • 161

    Analog Input Enable Register (ADER)

163

Chapter 8 Time-Based Timer

• 164

  Overview of the Time-Based Timer
• 165

  Time-Based Timer Control Register (TBTC)
• 167

  Time-Based Timer Operations

169

Chapter 9 Watchdog Timer

• 170

  Overview of the Watchdog Timer
• 171

  Watchdog Timer Control Register (WDTC)
• 173

  Watchdog Timer Operations

175

Chapter 10 16-Bit I/O Timer

• 176

  Overview of the 16-Bit I/O Timer
• 178

  16-Bit I/O Timer Block Diagram
• 179

  16-Bit I/O Timer Registers
  • 181

    16-Bit Free-Run Timer
  • 184

    Output Compare
  • 188

    Input Capture
• 190

  16-Bit Free-Run Timer Operations
• 192

  16-Bit Output Compare Operations
• 195

  16-Bit Input Capture Operations

198

Chapter 11 16-BIT RELOAD TIMER (WITH the EVENT COUNT FUNCTION)

• 198

  Overview of the 16-Bit Reload Timer (With the Event Count Function)
• 199

  Registers of the 16-Bit Reload Timer (With the Event Count Function)
  • 200

    Timer Control Status Register (TMCSR)
  • 203

    16-Bit Timer Register (TMR) and 16-Bit Reload Register (TMRLR)
• 204

  Clock Operations
• 205

  Underflow Operation
• 206

  I/O Pin Functions
• 208

  Counter Operation Statuses

209

Chapter 12 8/16-Bit Ppg

• 210

  Overview of the 8/16-Bit PPG
• 211

  Block Diagrams of the 8-Bit PPG
• 213

  Registers in the 8/16-Bit PPG
  • 214

    PPG0 Operation Mode Control Register (PPGC0)
  • 216

    PPG1 Operation Mode Control Register (PPGC1)
  • 219

    PPG0/1 Output Pin Control Register (PPGE)
  • 221

    Reload Registers (PRLL/PRLH)
• 222

  8/16-Bit PPG Operation
  • 224

    8/16-Bit PPG Operation Modes
  • 225

    PPG Output Operation
  • 227

    Selecting a Count Clock
  • 228

    Controlling Pulse Output On Pins
  • 229

    Write Timing for the Reload Registers

231

Chapter 13 Dtp/External Interrupt

• 232

  Overview of the Dtp/External Interrupt Circuit
• 234

  Registers in the Dtp/External Interrupt Circuit
• 237

  Operation of Dtp/External Interrupt Circuit
• 240

  Notes On Using the Dtp/External Interrupt Circuit

243

Chapter 14 Delayed Interrupt Generating Module

• 244

  Outline of the Delayed Interrupt Generating Module
• 245

  Operation of the Delayed Interrupt Generating Module

247

Chapter 15 A/D Converter

• 248

  Overview of the A/D Converter
• 251

  Resisters of the A/D Converter
  • 252

    Control Status Registers (ADCS0 and ADCS1)
  • 256

    Data Register (ADCR1 and ADCR0)
• 258

  Operation of A/D Converter
  • 260

    Example of EI OS Activation in Single Mode
  • 262

    Example of EI OS Activation in Successive Mode
  • 262

    Example of EI 2 OS Activation in Successive Mode
  • 264

    Example of EI OS Activation in Pause Mode
  • 264

    Example of EI 2 OS Activation in Pause Mode
• 266

  Conversion Data Protection Function

269

Chapter 16 Communication Prescaler Register

• 270

  Overview of Communication Prescaler Register
• 272

  Operation of Communication Prescaler Register

273

Chapter 17 Uart

• 274

  Overview of UART
• 275

  UART Block Diagram
• 276

  UART Registers
  • 277

    Serial Mode Register (SMR)
  • 279

    Serial Control Register (SCR)
  • 282

    Serial Input Data Register (SIDR) and Serial Output Data Register (SODR)
  • 283

    Serial Status Register (SSR)
• 286

  UART Operations
  • 287

    UART Clock Selection
  • 289

    Asynchronous (Start-Stop Synchronous) Mode
  • 291

    Clk-Synchronous Mode
  • 293

    Occurrence of Interrupt and Flag Setting Timing
• 296

  Application of UART (During Operation in Mode 1)

299

Chapter 18 I/O Extended Serial Interface

• 300

  Overview of the I/O Extended Serial Interface
• 302

  Registers of the I/O Extended Serial Interface
  • 303

    Serial Mode Control Status Register (SMCS)
  • 307

    Serial Shift Data Register (SDR)
• 308

  Operation of I/O Extended Serial Interface
  • 309

    Shift Clock
  • 311

    Operation States of the Serial I/O
  • 313

    Start/Stop Timing of Shift Operation and Input/Output Timing
  • 316

    Interrupt Function of the I/O Extended Serial Interface

318

Chapter 19 I 2 C Interface

• 318

  C Interface
  • 319

    Block Diagram and Structure of the I
• 319

  C Interface
• 321

  Registers of the I C Interface
  • 322

    Bus Status Register (IBSR)
  • 325

    Bus Control Register (IBCR)
  • 328

    Clock Control Register (ICCR)
  • 330

    Address Register (IADR)
  • 331

    Data Register (IDAR)
  • 332

    Port Selection Register (ISEL)
• 333

  Operation of the I C Interface
  • 335

    Flow of the I 2 C Interface Transmission
  • 337

    Flow of the I C Interface Modes

339

Chapter 20 Clock Monitor Function

• 340

  Overview of the Clock Monitor Functions
• 341

  Clock Output Permission Register (CLKR)

343

Chapter 21 Address Match Detection Function

• 344

  Overview of the Address Match Detection Function
• 345

  Registers of the Address Match Detection Function
• 347

  Operation of the Address Match Detection Function
• 348

  Example of the Address Match Detection Function
• 350

  Program Example of the Address Match Detection Function

353

Chapter 22 Rom Mirror Function Selection Module

• 354

  Overview of the ROM Mirror Function Selection Module
• 355

  ROM Mirror Function Selection Register (ROMM)

357

Chapter 23 1M-Bit Flash Memory

• 358

  Overview of the 1M-Bit Flash Memory
• 359

  Block Diagram and Sector Configuration of the Entire Flash Memory
• 361

  Writing and Deletion Modes
• 363

  Flash Memory Control Status Register (FMCS)
• 365

  Activating the Automatic Algorithm of the Flash Memory
• 366

  Confirming the Automatic Algorithm Execution Status
  • 368

    Data Polling Flag (DQ7)
  • 370

    Toggle Bit Flag (DQ6)
  • 371

    Timing Limit Excess Flag (DQ5)
  • 372

    Sector Deletion Timer Flag (DQ3)
• 373

  Detailed Explanations of Flash Memory Writing and Deletion
  • 374

    Setting the Flash Memory in the Read or Reset Status
  • 375

    Writing Data in the Flash Memory
  • 377

    Deleting All Data Items From the Flash Memory (Chip Deletion)
  • 378

    Deleting Any Data Item From the Flash Memory (Sector Deletion)
  • 380

    Temporarily Stopping the Sector Deletion From the Flash Memory
  • 381

    Restarting the Flash Memory Sector Deletion
• 382

  Example of the 1M-Bit Flash Memory Program

387

Chapter 24 Example of Mb90F553A Serial Programming Connection

• 388

  Basic Configuration of MB90F553A Serial Programming Connection
• 391

  Example of Serial Programming Connection (When User Power Supply Is Used)
• 393

  Example of Serial Programming Connection (When Power Is Supplied From a Writer)
  • 395

    (When User Power Supply Is Used)
• 397

  Example of Minimal Connection With the Flash Microcontroller Programmer (When Power Is Supplied From a Writer)

399

Appendix

400

Appendix A I/O Map

408

APPENDIX B Instructions

• 409

  Instruction Types
• 409

  B.1 Instruction Types
• 410

  Addressing
• 410

  B.2 Addressing
• 412

  Direct Addressing
• 412

  B.3 Direct Addressing
• 418

  Indirect Addressing
• 418

  B.4 Indirect Addressing
• 426

  Execution Cycle Count
• 429

  Effective Address Field
• 430

  How to Read the Instruction List
• 433

  F 2 MC-16LX Instruction List
• 447

  Instruction Map
• 447

  B.9 Instruction Map