Fujitsu MB96300 series Hardware Manual page 831

MB96300 Super Series Hardware Manual
Table 31.2-1 Function of each bit of the PFCS0 (MPF channel 0 and 1)
Name
bit 2
bit 1
bit 0
IE0 This is an enable bit for the interrupt flag I0. It controls the hardware interrupt
generation of MPF channel 0. This is used to implement a operand break feature.
• Writing '0' - The interrupt is disabled.
• Writing '1' - The interrupt is enabled. In case of an address, type or data value
match, an INT9 hardware interrupt is asserted.
• If the PE0 bit is set in addition, the channel 0 operates as data value break. An
additional data match is required to assert INT9.
• The bit can be read and written.
The IE0 bit is cleared after reset.
I1 This is the match indication/interrupt flag for channel 1. The address match
condition can be combined with the access type match. Once set, the bit remains
set until cleared by software.
• Reading '0' - Indicates that there was no match since last clear operation.
• Reading '1' - Indicates that at least one match has occurred since last clear
operation. If IE1 is set, an interrupt is issued. If PE1 is set and IE1 is cleared, the
read data on the bus are replaced by PFD1.
• Writing '0' clears the bit
• Writing '1' has no effect
• A RMW instruction reads always '1'
If a write access to the I flag and a hardware event, which sets the I flag, occures at
the same time, the hardware event has precedence.
If either AM or AR is set, no match is generated on MPF channel 1. Thus the I1
flag will not be set in that case.
This bit is cleared after reset.
Before enabling the interrupt function (IE1=1), it is recommended to clear the I1
bit.
I0 This is the match indication/interrupt flag for channel 0. The address match
condition can be combined with access type and data value matches. Once set, the
bit remains set until cleared by software.
• Reading '0' - Indicates that there was no match since last clear operation.
• Reading '1' - Indicates that at least one match has occurred since last clear
operation. If IE0 is set, an interrupt is issued. If PE0 is set and IE0 is cleared, the
read data on the bus are replaced by PFD0.
• Writing '0' clears the bit
• Writing '1' has no effect
• A RMW instruction reads always '1'
If a write access to the I flag and a hardware event, which sets the I flag, occures at
the same time, the hardware event has precedence.
This bit is cleared after reset.
Before enabling the interrupt function (IE0=1), it is recommended to clear the I0
bit.
CHAPTER 31 MEMORY PATCH FUNCTION
Function
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