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Fujitsu MB91150 Series Manuals
Manuals and User Guides for Fujitsu MB91150 Series. We have
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Fujitsu MB91150 Series manual available for free PDF download: Hardware Manual
Fujitsu MB91150 Series Hardware Manual (512 pages)
32-bit microcontroller
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 7.55 MB
Table of Contents
Table of Contents
11
Chapter 1 Overview of the Mb91150
17
MB91150 Features
18
Block Diagrams
21
Package Dimensions
23
Pin Assignment
25
Pin Functions
28
I/O Circuit Types
36
Chapter 2 Handling the Device
39
Notes on Handling Devices
40
Notes on Using Devices
42
Power-On
43
Chapter 3 Memory Space, Cpu and Control Unit
45
Memory Space
46
CPU Architecture
49
Programming Model
52
Data Structure
60
Word Alignment
61
Special Memory Areas
62
Overview of Instructions
63
Operations with Delay Slots
65
Branch Instructions Without a Delay Slot
68
EIT (Exception, Interrupt, and Trap)
69
Interrupt Level
70
Interrupt Stack Operation
71
EIT Vector Table
72
Multiple EIT Processing
74
EIT Operation
76
Reset Sequence
80
Operation Mode
81
Clock Generator (Low-Power Consumption Mechanism)
83
Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR)
85
Standby Control Register (STCR)
87
Time-Base Timer Clear Register (CTBR)
88
Gear Control Register (GCR)
89
Watchdog Reset Generation Delay Register (WPR)
91
DMA Request Suppression Register (PDRR)
92
PLL Control Register (PCTR)
93
Watchdog Function
94
Gear Function
96
Retaining a Reset Source
98
Example of Setting the PLL Clock
100
Low-Power Consumption Mode
103
Stop Status
105
Sleep Status
108
Status Transition of the Low-Power Consumption Mode
111
Chapter 4 Bus Interface
113
Outline of Bus Interface
114
Block Diagram of the Bus Interface
116
Registers of the Bus Interface
117
Area Select Registers (ASR) and Area Mask Registers (AMR)
118
Area Mode Register 0 (AMD0)
120
Area Mode Register 1 (AMD1)
122
Area Mode Register 32 (AMD32)
123
Area Mode Register 4 (AMD4)
124
Area Mode Register 5 (AMD5)
125
External Pin Control Register 0 (EPCR0)
126
External Pin Control Register 1 (EPCR1)
128
Little-Endian Register (LER)
129
Bus Operation
130
Relationship between Data Bus Width and Control Signals
131
Bus Access in Big-Endian Mode
132
Bus Access in Little-Endian Mode
138
Comparison of External Access in Big-Endian and Little-Endian Mode
142
Bus Timing
147
Basic Read Cycle
148
Basic Write Cycle
150
Read Cycle in each Mode
152
Write Cycle in each Mode
154
Mixed Read/Write Cycles
156
Automatic Wait Cycle
157
External Wait Cycle
158
External Bus Request
159
Internal Clock Multiply Operation (Clock Doubler)
160
Program Examples for the External Bus
162
Chapter 5 I/O Ports
165
Overview of I/O Ports
166
Block Diagram of Basic I/O Port
167
Block Diagram of I/O Ports (Including the Pull-Up Resistor)
168
Block Diagram of I/O Ports (Including the Open-Drain Output and the Pull-Up Resistor)
169
Block Diagram of I/O Port (with Open-Drain Output Function)
171
Port Data Register (PDR)
172
Data Direction Register (DDR)
173
Pull-Up Control Register (PCR)
175
Open-Drain Control Register (ODCR)
176
Analog Input Control Register (AICR)
177
Chapter 6 8/16-Bit Up/Down Counter/Timer
179
Overview of 8/16-Bit Up/Down Counter/Timer
180
Block Diagram of the 8/16-Bit Up/Down Counter/Timer
182
List of Registers of the 8/16-Bit Up/Down Counter/Timer
184
Counter Control Register H/L (CCRH/L)
185
Counter Control Register H/L Ch1 (CCR H/L Ch1)
189
Counter Status Register 0/1 (CSR0/1)
190
Up/Down Count Register 0/1 (UDCR 0/1)
192
Reload/Compare Register 0/1 (RCR 0/1)
193
Selection of Counting Mode
194
Reload and Compare Functions
197
Writing Data to the Up/Down Count Register (UDCR)
201
Chapter 7 16-Bit Reload Timer
203
Overview of 16-Bit Reload Timer
204
Block Diagram of a 16-Bit Reload Timer
205
Registers of 16-Bit Reload Timer
206
Control Status Register (TMCSR)
207
16-Bit Timer Register (TMR) and 16-Bit Reload Register (TMRLR)
209
Internal Clock Operation
210
Underflow Operation
211
Counter Operation States
213
Chapter 8 Ppg Timer
215
Overview of PPG Timer
216
Block Diagram of PPG Timer
217
Registers of PPG Timer
219
Control Status Registers (PCNH, PCNL)
221
PWM Cycle Set Register (PCSR)
225
PWM Duty Set Register (PDUT)
226
PWM Timer Register (PTWR)
227
General Control Register 1 (GCN1)
228
General Control Register 2 (GCN2)
231
PWM Operation
232
One-Shot Operation
234
PWM Timer Interrupt Source and Timing Chart
236
Activating Multiple Channels by Using the General Control Register (GCN)
238
Chapter 9 Multifunctional Timer
241
Overview of Multifunctional Timer
242
Block Diagram of the Multifunctional Timer
244
Registers of Multifunctional Timer
245
Registers of 16-Bit Free-Run Timer
246
Registers of the Output Compare
250
Registers of Input Capture
253
Operations of Multifunctional Timer
255
Operation of 16-Bit Free-Run Timer
256
Operation of 16-Bit Output Compare
258
Operation of 16-Bit Input Capture
261
Chapter 10 External Interrupt Control Block
263
Overview of External Interrupt
264
External Interrupt Registers
265
Enable Interrupt Register (Enirn)
266
External Interrupt Request Register (Eirrn)
267
External Interrupt Level Setting Register (ELVR: External Level Register)
268
External Interrupt Operation
269
External Interrupt Request Level
270
Chapter 11 Delayed Interrupt Module
271
Overview of Delayed Interrupt Module
272
Delayed Interrupt Control Register (DICR)
273
Operation of Delayed Interrupt Module
274
Chapter 12 Interrupt Controller
275
Overview of Interrupt Controller
276
Block Diagram of the Interrupt Controller
277
List of Interrupt Controller Registers
278
Interrupt Control Register (ICR)
280
Hold-Request Cancellation-Request Level-Set Register (HRCL)
282
Priority Evaluation
283
Return from Standby (Stop or Sleep) Mode
285
Hold-Request Cancellation Request
286
Example of Using Hold-Request Cancellation-Request Function (HRCR)
287
Chapter 13 8/10-Bit A/D Converter
291
Overview of the 8/10-Bit A/D Converter
292
8/10-Bit A/D Converter Block Diagram
293
8/10-Bit A/D Converter Pins
295
8/10-Bit A/D Converter Registers
297
A/D Control Status Register 1 (ADCS1)
298
A/D Control Status Register 0 (ADCS0)
301
A/D Data Register (ADCR)
303
8/10-Bit A/D Converter Interrupt
305
Operation of the 8/10-Bit A/D Converter
306
A/D Converted Data Preservation Function
308
Notes on Using the 8/10-Bit A/D Converter
309
Chapter 14 8-Bit D/A Converter
311
Overview of the 8-Bit D/A Converter
312
8-Bit D/A Converter Block Diagram
313
8-Bit D/A Converter Registers
314
D/A Control Registers (DACR0, DACR1, DACR2)
315
D/A Data Registers (DADR2, DADR1, DADR0)
316
8-Bit D/A Converter Operation
317
Chapter 15 Uart
319
Overview of the UART
320
UART Block Diagram
322
UART Pins
324
UART Registers
327
Control Register (SCR0-3)
328
Mode Register (SMR0-3)
330
Status Register (SSR0-3)
332
Input-Data Register (SIDR0-3), Output-Data Register (SODR0-3)
334
Communication Prescaler Control Register (CDCR)
336
Interrupts
338
Receive-Interrupt Generation and Flag Set Timing
340
Send-Interrupt Generation and Flag Set Timing
341
Baud Rate
342
Baud Rate Based on the Dedicated Baud-Rate Generator
344
Baud Rate Based on the Internal Timer (16-Bit Reload Timer 0)
347
Baud Rate Based on the External Clock
349
UART Operations
350
Operation in Asynchronous Mode (Operation Modes 0 to 1)
352
Operation in Synchronous Mode (Operation Mode 2)
355
Bidirectional Communication Function (Normal Mode)
357
Master/Slave-Type Communication Function (Multiprocessor Mode)
359
Notes on Using UART
361
Chapter 16 I 2 C Interface
364
Overview of I C Interface
364
Block Diagram of I C Interface
365
Registers of I C Interface
366
Bus Control Register (IBCR)
367
Bus Status Register (IBSR)
370
Address Register (Iadr)/Data Register (IDAR)
372
Clock Control Register (ICCR)
373
Operation of I C Interface
375
Chapter 17 Dma Controller
377
Overview of the DMA Controller Overview
378
Block Diagram of the DMA Controller
379
Registers of the DMA Controller
380
DMAC Parameter Descriptor Pointer (DPDP)
381
MAC Control Status Register (DACSR)
382
DMAC Pin Control Register (DATCR)
384
Register of the Descriptor in RAM
386
Transfer Modes Supported by the DMA Controller
389
Step Transfer (Single/Block Transfer)
392
Continuos Transfer
393
Burst Transfer
394
Differences Because of DREQ Sense Mode
395
Transfer-Acceptance Signal Output and Transfer-End Signal Output
397
Notes on the DMA Controller
398
Timing Charts for the DMA Controller
400
Timing Charts for the Descriptor Access Section
401
Timing Charts for the Data Transfer Section
403
Timing Charts for Transfer Termination in Continuous Transfer Mode
405
Timing Charts for the Transfer Termination Operation
407
Chapter 18 Bit-Search Module
409
Overview of the Bit-Search Module
410
Registers of the Bit-Search Module
411
Operation of the Bit-Search Module
413
Chapter 19 Peripheral Stop Control
415
Overview of Peripheral Stop Control
416
Peripheral Stop Control Registers
417
Chapter 20 Calendar Macros
421
Overview of Calendar Macros
422
Calendar Macro Registers
423
Calendar Macro Operation
427
Chapter 21 Flash Memory
429
Overview of Flash Memory
430
Flash Memory Registers
434
Flash Memory Operation
437
Automatic Algorithm of Flash Memory
439
Checking the Automatic Algorithm Execution Status
443
Writing and Erasing Flash Memory
448
Putting Flash Memory into Read/Reset Status
449
Writing Data to Flash Memory
450
Erasing Data
452
Temporarily Stopping and Restarting Sector Erase
454
Appendix
455
APPENDIX A I/O Map
456
APPENDIX B Interrupt Vectors
464
APPENDIX C Pin Status in each CPU State
468
APPENDIX D Notes on Using the Little-Endian Area
475
C Compiler (Fcc911)
476
Assembler (Fasm911)
479
Linker (Flnk911)
480
Debuggers (Sim911, Eml911, and Mon911)
481
APPENDIX E Instruction Lists
482
Index
503
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