Table of Contents
Advertisement
CHAPTER 3 INTERRUPTS
processing, if an active signal level is detected at the NMI pin (defined by the LEV bit).
If EN is set to '1', both the LEV and EN bits are locked for writing. Neither the signal level can be
changed nor the NMI can be disabled after the NMI feature was enabled once. Only a device reset can
change the EN bit back to '0'.
At reset the EN bit is initialized to '0', thus the NMI feature is not enabled by default.
The LEV and EN bits must not be activated at same time (changed using the same access). EN must be
enabled individually at last. Otherwise, an NMI can be caused due to relaxation time of the spike filter.
NMI [bit 8]: FLAG - Non Maskable Interrupt Flag
The NMI FLAG stores an asynchronous event of the NMI occurrence at the NMI pin.
A spike filter is used to filter out short pulses for spike suppression. The polarity of the pulses depends on
the definition in the LEV bit.
The NMI flag is set by the hardware event (NMI occurrence) and can be cleared by software to quit the
interrupt. An interrupt is only caused, if both the EN bit and FLAG are set.
The NMI FLAG can be read and cleared. Writing '1' to FLAG is ignored.
The NMI FLAG is undefined after reset. Before enabling the NMI, this flag should be cleared.
For bit manipulation, an RMW-read operation returns always '1' for this flag.
16FX Bus
NMI pin
level selection
and spike filter
ASET: asynchronous set
SCLR: synchronous clear
98
Figure 3.4-2 Operation of the NMI control/status register
EN
NMI LEV
lock function
[10]
EN
NMI EN
[9]
[8]
ASET
NMI FLAG
SCLR
MB96300 Super Series Hardware Manual
CLKB
Synchronization
0
1
SLEEP || STOP || TIMER
NMI to CPU
Wakeup
Advertisement
Table of Contents
