Fujitsu FR Family FR60 Lite Manuals

Manuals and User Guides for Fujitsu FR Family FR60 Lite. We have 5 Fujitsu FR Family FR60 Lite manuals available for free PDF download: User Manual, Hardware Manual

Fujitsu FR Family FR60 Lite User Manual (1038 pages)

32-BIT MICROCONTROLLER

Brand: Fujitsu | Category: Computer Hardware | Size: 11.01 MB

Table of Contents
5
Chapter 1 Introduction

17
- How to Handle the Device
  17
- Instruction for Users
  19
- Caution: Debug-Related Matters
  22
- How to Use this Document
  23
Chapter 2 MB91460 Rev.a/Rev.b Overview

27
- Overview
  27
- Features
  27
- MB91460 Series Product Lineup
  35
- Block Diagram
  37
Chapter 3 MB91460 Series Basic Information

39
- Memory Map
  39
- I/O Map
  40
- Interrupt Vector Table
  89
- Package
  94
- Pin Assignment Diagram
  95
- Pin Definitions
  96
- I/O Circuit Type
  110
- Pin State Table
  112
Chapter 4 CPU Architecture

121
- Overview
  121
- Features
  122
- Cpu
  123
- Bit/16-Bit Bus Converter
  123
- Harvard/Princeton Bus Converter
  123
- Instruction Overview
  124
- Data Structure
  125
- Word Alignment
  126
- Addressing
  127
Chapter 5 CPU Registers

129
- General-Purpose Registers
  129
- Dedicated Registers
  129
Chapter 6 EIT: Exceptions, Interrupts and Traps

137
- Overview
  137
- Features
  137
- EIT Trigger
  137
- Return from EIT
  137
- EIT Interrupt Level
  138
- EIT Vector Table
  138
- Multiple EIT Processing
  139
- Operation
  141
- Caution
  144
Chapter 7 Branch Instruction

145
Chapter 8 Device State Transition

149
- Overview
  149
- Features
  149
- State Transition Diagram
  150
Chapter 9 Reset

155
- Overview
  155
- Features
  155
- Configuration
  156
- Registers
  157
- INIT Pin Input (INIT: Settings Initialization Reset)
  162
- Watchdog Reset (INIT: Settings Initialization Reset)
  164
- Software Reset (RST: Operation Initialization Reset)
  165
- Reset Operation Modes
  166
- MCU Operation Mode
  167
- Caution
  168
Chapter 10 Standby

171
- Overview
  171
- Features
  171
- Configuration
  172
- Registers
  173
- Operation
  175
- Settings
  177
- Caution
  181
Chapter 11 Memory Controller

183
- Overview
  183
- FLASH Interface
  183
- General Purpose RAM
  183
- Instruction Cache and Data Buffer
  183
- Prefetch
  183
- Fixed Mode and Reset Vectors
  183
- Registers
  184
- Explanations of Registers
  185
Chapter 12 Instruction Cache

195
- General Description
  195
- Main Body Structure
  195
- Operating Mode Conditions
  201
- Cacheable Areas in the Instruction Cache
  202
- Settings for Handling the I-Cache
  202
Chapter 13 Clock Control

205
- Overview
  205
- Features
  205
- Configuration
  206
- Registers
  207
- Operation
  215
- Settings
  217
- Caution
  221
Chapter 14 PLL Interface

223
- Overview
  223
- Features
  223
- Frequency Calculation
  223
- Registers
  224
- Recommended Settings
  228
- Clock Auto Gear Up/Down
  229
- Caution
  231
Chapter 15 CAN Clock Prescaler

233
- Overview
  233
- Features
  233
- Registers
  234
Chapter 16 Clock Supervisor

237
- Overview Clock Supervisor
  237
- Clock Supervisor Register
  238
- Block Diagram Clock Supervisor
  240
- Operation Modes
  241
- Stop Mode
  252
Chapter 17 Clock Modulator

255
- Overview
  255
- Clock Modulator Registers
  256
- Application Note
  263
Chapter 18 Timebase Counter

265
- Overview
  265
- Features
  265
- Configuration
  266
- Registers
  267
- Operation
  269
- Settings
  275
- Caution
  278
Chapter 19 Timebase Timer

279
- Overview
  279
- Features
  279
- Configuration
  280
- Register
  281
- Operation
  283
- Setting
  284
- Caution
  287
Chapter 20 Software Watchdog Timer

289
- Overview
  289
- Features
  289
- Configuration
  290
- Register
  291
- Operation
  294
- Setting
  296
- Caution
  298
Chapter 21 Hardware Watchdog Timer

299
- Overview
  299
- Configuration
  300
- Register
  301
- Functions
  303
- Caution
  304
Chapter 22 Main Oscillation Stabilisation Timer

305
- Overview
  305
- Features
  305
- Configuration
  306
- Register
  307
- Operation
  308
- Setting
  310
- Caution
  313
Chapter 23 Sub Oscillation Stabilisation Timer

315
- Overview
  315
- Features
  315
- Configuration
  316
- Register
  317
- Operation
  319
- Setting
  322
- Caution
  325
Chapter 24 Interrupt Control

327
- Overview
  327
- Features
  327
- Configuration
  328
- Registers
  329
- Interrupt Vector
  333
- Operation
  334
- Setting
  335
- Caution
  336
Chapter 25 External Interrupt

337
- Overview
  337
- Features
  337
- Configuration
  338
- External Interrupts
  339
- Registers
  341
- Operation
  343
- Setting
  344
- Interrupt Types
  345
- Caution
  347
Chapter 26 DMA Controller

349
- Overview of the DMA Controller (DMAC)
  349
- DMA Controller (DMAC) Registers
  351
- DMA Controller (DMAC) Operation
  370
- Operation Flowcharts
  389
- Data Bus
  392
- DMA External Interface
  395
Chapter 27 Delayed Interrupt

399
- Overview
  399
- Features
  399
- Configuration
  399
- Register
  400
- Operation
  400
- Setting
  401
- Caution
  401
Chapter 28 Bit Search

403
- Overview
  403
- Features
  403
- Configuration
  404
- Register
  405
- Operation
  407
- Setting
  409
- Caution
  411
Chapter 29 MPU / EDSU

413
- Overview
  413
- Features
  414
- Break Functions
  415
- Memory Protection
  420
- Registers
  423
- Quick Reference
  445
Chapter 30 I/O Ports

447
- I/O Ports Functions
  447
- I/O Circuit Types
  469
- Port Register Settings
  470
Chapter 31 External Bus

523
- Overview of the External Bus Interface
  523
- External Bus Interface Registers
  528
- Setting Example of the Chip Select Area
  558
- Endian and Bus Access
  559
- Operation of the Ordinary Bus Interface
  578
- Burst Access Operation
  590
- Address/Data Multiplex Interface
  592
- Prefetch Operation
  595
- SDRAM/FCRAM Interface Operation
  598
- Self Refresh
  600
- DMA Access Operation
  608
- Bus Arbitration
  624
- Procedure for Setting a Register
  626
- Notes on Using the External Bus Interface
  627
Chapter 32 USART (LIN / FIFO)

629
- Overview
  629
- Usart Interrupts
  631
- USART Configuration
  632
- USART Pins
  636
- USART Registers
  637
- USART Interrupts
  654
  - Reception Interrupt Generation and Flag Set Timing
    656
  - Transmission Interrupt Generation and Flag Set Timing
    657
- USART Baud Rates
  658
  - Setting the Baud Rate
    659
  - Restarting the Reload Counter
    661
- USART Operation
  663
  - Error Detection
    667
  - Direct Access to Serial Pins
    670
- Notes on Using USART
  679
Chapter 33 I2C Controller

681
- Overview
  681
- I2C Interface Registers
  683
- I2C Interface Operation
  701
- Programming Flow Charts
  703
Chapter 34 CAN Controller

707
- Overview
  707
- Register Description
  708
- Functional Description
  736
- CAN Application
  740
Chapter 35 Free-Run Timer

749
- Overview
  749
- Features
  749
- Configuration Diagram
  750
- Registers
  751
- Operation
  755
- Setting
  757
- Caution
  761
Chapter 36 Input Capture

763
- Overview
  763
- Features
  763
- Configuration
  764
- Register
  765
- Operation
  768
- Settings
  770
- Caution
  774
Chapter 37 Output Compare

775
- Overview
  775
- Features
  775
- Configuration Diagram
  776
- Registers
  777
- Operation
  781
- Settings
  783
- Caution
  789
Chapter 38 Reload Timer

791
- Overview
  791
- Features
  791
- Configuration
  792
- Registers
  794
- Operation
  798
- Setting
  803
- Caution
  810
Chapter 39 Programmable Pulse Generator

811
- Overview
  811
- Features
  811
- Configuration
  813
- Registers
  815
- Operation
  824
- Setting
  827
- Caution
  837
Chapter 40 Pulse Frequency Modulator

839
- PFM Overview
  839
- Reload Counter Registers
  842
- Reload Counter Operation
  846
- PFM Operation and Setting
  849
Chapter 41 Up/Down Counter

851
- Overview
  851
- Feature
  851
- Configuration
  852
- Register
  856
- Operation
  864
- Setting
  871
- Caution
  878
Chapter 42 Sound Generator

879
- Overview
  879
- Block Diagram
  880
- Registers
  881
Chapter 43 Stepper Motor Controller

887
- Overview
  887
- Registers
  888
- Operation
  897
- Caution
  899
Chapter 44 A/D Converter

901
- Overview of A/D Converter
  901
- Block Diagram of A/D Converter
  902
- Registers of A/D Converter
  903
- Operation of A/D Converter
  912
- Setting
  915
- Caution
  922

Fujitsu FR Family FR60 Lite Hardware Manual (664 pages)

Brand: Fujitsu | Category: Microcontrollers | Size: 3.88 MB

Table of Contents
9
Chapter 1 Overview

19
- Features
  20
- Block Diagram
  25
- Package Dimensions
  27
- Pin Layout
  29
- List of Pin Functions
  31
- Input-Output Circuit Forms
  45
Chapter 2 Handling the Device

49
- Precautions on Handling the Device
  50
- Precautions on Using the Little-Endian Area
  55
  - C Compiler (Fcc911)
    56
  - Assembler (Fasm911)
    59
  - Linker (Flnk911)
    60
  - Debuggers (Sim911, Eml911, and Mon911)
    61
Chapter 3 Cpu and Control Units

63
- Memory Space
  64
- Internal Architecture
  67
  - Internal Architecture
    68
  - Overview of Instructions
    71
- Programming Model
  73
  - General-Purpose Registers
    74
  - Dedicated Registers
    75
- Data Configuration
  82
- Memory Map
  84
- Branch Instructions
  85
  - Operations with a Delay Slot
    86
  - Operation Without Delay Slot
    89
- EIT (Exception, Interrupt, and Trap)
  90
  - EIT Interrupt Levels
    91
  - ICR (Interrupt Control Register)
    93
  - SSP (System Stack Pointer)
    95
  - Interrupt Stack
    96
  - TBR (Table Base Register)
    97
  - EIT Vector Table
    98
  - Multiple EIT Processing
    102
  - Operations
    104
- Operating Modes
  108
  - Bus Modes
    109
  - Mode Settings
    110
- Reset (Device Initialization)
  112
  - Reset Levels
    113
  - Reset Sources
    114
  - Reset Sequence
    116
  - Oscillation Stabilization Wait Time
    117
  - Reset Operation Modes
    120
- Clock Generation Control
  122
  - PLL Controls
    123
  - Oscillation Stabilization Wait Time and PLL Lock Wait Time
    124
  - Clock Distribution
    126
  - Clock Division
    128
  - Block Diagram of Clock Generation Controller
    129
  - Register of Clock Generation Controller
    130
  - Peripheral Circuits of Clock Controller
    147
- Device State Control
  151
  - Device States and State Transitions
    152
  - Low-Power Consumption Modes
    156
- Watch Timer
  161
- Main Clock Oscillation Stabilization Wait Timer
  167
- Peripheral Stop Control
  173
Chapter 4 External Bus Interface

179
- Overview of the External Bus Interface
  180
- External Bus Interface Registers
  185
- Setting Example of the Chip Select Area
  204
- Byte Ordering (Endian) and Bus Access
  206
  - Relationship between Data Bus Widths and Control Signals
    207
  - Big Endian Bus Access
    208
  - Little Endian Bus Access
    215
  - External Access
    219
- Ordinary Bus Interface
  223
- Address/Data Multiplex Interface
  233
- Prefetch Operation
  236
- DMA Access Operation
  240
- Bus Arbitration
  246
- Procedure for Setting a Register
  248
Chapter 5 I/O Port

249
- Overview of the I/O Port
  250
- I/O Port Registers
  252
CHAPTER 6 8/16-Bit Up/Down Counters/Timer and U-Timers

263
- 8/16-Bit Up/Down Counters/Timers
  264
- U-Timer
  286
  - Overview of the U-TIMER
    287
  - U-TIMER Registers
    288
  - Operation of the U-TIMER
    293
Chapter 7 16-Bit Free-Running Timer and 16-Bit Reload Timer

296
- 16-Bit Free-Running Timer
  296
- 16-Bit Reload Timer
  304
Chapter 8 Programmable Pulse Generator (Ppg) Timer

315
Chapter 9 Interrupt Controller

341
Chapter 10 External Interrupt and Nmi Controller

359
Chapter 11 Realos-Related Hardware

369
- Delayed Interrupt Module
  370
- Bit Search Module
  374
Chapter 12 A/D Converter

381
- Overview of the A/D Converter
  382
- A/D Converter Registers
  384
- Operation of the A/D Converter
  394
Chapter 13 8-Bit D/A Converter

394
Chapter 14 Uart, Serial I/O Interface (Sio), Input Capture Module, and Output Compare Module

403
- Uart
  404
  - Features of the UART
    405
  - UART Registers
    408
  - Operation of the UART
    417
  - Example of Using the UART
    425
- Serial I/O Interface (SIO)
  428
- Input Capture Module
  443
  - Overview of the Input Capture Module
    444
  - Input Capture Module Registers
    446
  - Input Capture Operation
    448
- Output Compare
  449
Chapter 15 I 2 C Interface

457
- Overview of the I 2 C Interface
  458
- C Interface Registers
  462
  - Bus Status Register (IBSR)
    463
  - Bus Control Register (IBCR)
    466
  - Clock Control Register (ICCR)
    473
  - 10-Bit Slave Address Register (ITBA)
    475
  - 10-Bit Slave Address Mask Register (ITMK)
    476
  - 7-Bit Slave Address Register (ISBA)
    478
  - 7-Bit Slave Address Mask Register (ISMK)
    479
  - Data Register (IDAR)
    480
  - Clock Disable Register (IDBL)
    481
- Explanation of I 2 C Interface Operation
  482
- Operation Flowcharts
  486
Chapter 16 Dma Controller (Dmac)

489
- Overview
  490
- Detailed Explanation of Registers
  493
- Explanation of Operation
  510
  - Overview of Operation
    511
  - Setting a Transfer Request
    514
  - Transfer Sequence
    515
  - General Aspects of DMA Transfer
    519
  - Addressing Mode
    521
  - Data Types
    522
  - Transfer Count Control
    523
  - CPU Control
    524
  - Hold Arbitration
    525
  - Operation from Starting to End/Stopping
    526
  - Transfer Request Acceptance and Transfer
    527
  - Clearing Peripheral Interrupts by DMA
    528
  - Temporary Stopping
    529
  - Operation End/Stopping
    530
  - Stopping Due to an Error
    531
  - DMAC Interrupt Control
    532
  - DMA Transfer During Sleep
    533
  - Channel Selection and Control
    534
  - Supplement on External Pin and Internal Operation Timing
    536
- Operation Flowcharts
  540
- Data Path
  543
- DMA External Interface
  547

Fujitsu FR Family FR60 Lite Hardware Manual (636 pages)

32-BIT MICROCONTROLLER MB91301 Series

Brand: Fujitsu | Category: Microcontrollers | Size: 5.15 MB

Table of Contents
11
Chapter 1 Overview

21
- Features of the MB91301 Series
  22
- Block Diagram
  27
- Package Dimensions
  28
- Pin Layout
  31
- Pin No. Table
  33
- List of Pin Functions
  35
- I/O Circuit Types
  46
Chapter 2 Handling the Device

51
- Precautions on Handling the Device
  52
- Precautions on Handling Power Supplies
  59
Chapter 3 Cpu and Control Units

61
- Memory Space
  62
- Internal Architecture
  65
- Instruction Cache
  70
- Dedicated Registers
  83
  - Program Status (PS) Register
    86
- General-Purpose Registers
  90
- Data Structure
  91
- Word Alignment
  92
- Memory Map
  93
- Branch Instructions
  94
  - Operation of Branch Instructions with Delay Slot
    95
  - Operation of Branch Instruction Without Delay Slot
    98
- EIT (Exception, Interrupt, and Trap)
  99
  - EIT Interrupt Levels
    100
  - Interrupt Control Register (ICR)
    102
  - System Stack Pointer (SSP)
    103
  - Table Base Register (TBR)
    104
  - Multiple EIT Processing
    108
  - EIT Operations
    110
- Reset (Device Initialization)
  114
  - Reset Levels
    115
  - Reset Sources
    116
  - Reset Sequence
    118
  - Oscillation Stabilization Wait Time
    119
  - Reset Operation Modes
    121
- Clock Generation Control
  123
  - PLL Controls
    124
  - Oscillation Stabilization Wait Time and PLL Lock Wait Time
    125
  - Clock Distribution
    126
  - Clock Division
    128
  - Block Diagram of Clock Generation Controller
    129
  - Register of Clock Generation Controller
    130
  - Peripheral Circuits of Clock Controller
    145
  - Smooth Startup and Stop of Clock
    148
- Device State Control
  151
  - Device States and State Transitions
    153
  - Low-Power Modes
    156
- Operating Modes
  160
Chapter 4 External Bus Interface

163
- Overview of the External Bus Interface
  164
- External Bus Interface Registers
  169
- Setting Example of the Chip Select Area
  201
- Endian and Bus Access
  202
- Operation of the Ordinary Bus Interface
  222
  - Basic Timing
    223
  - Operation of Wrn + Byte Control Type
    224
  - Read -> Write Operation
    226
  - Write -> Write Operation
    227
  - Auto-Wait Cycle
    228
  - External Wait Cycle
    229
  - Synchronous Write Enable Output
    230
  - Csn Delay Setting
    232
  - Csn -> Rd/Wrn Setup and Rd/Wrn -> Csn Hold Setting
    233
  - DMA Fly-By Transfer (I/O -> Memory)
    234
  - DMA Fly-By Transfer (Memory -> I/O)
    235
- Burst Access Operation
  236
- Address/Data Multiplex Interface
  238
- Prefetch Operation
  241
- SDRAM/FCRAM Interface Operation
  244
  - Self Refresh
    248
  - Power-On Sequence
    249
  - Connecting SDRAM/FCRAM to Many Areas
    250
  - Address Multiplexing Format
    251
  - Memory Connection Example
    252
- DMA Access Operation
  256
- Bus Arbitration
  272
- Procedure for Setting a Register
  274
- Notes on Using the External Bus Interface
  275
Chapter 5 I/O Port

277
- Overview of the I/O Port
  278
- I/O Port Registers
  280
Chapter 6 16-Bit Reload Timer

289
Chapter 7 Ppg Timer

301
Chapter 8 U-Timer

327
- Overview of the U-TIMER
  328
- U-TIMER Registers
  329
- U-TIMER Operation
  333
Chapter 9 External Interrupt and Nmi Controller

335
Chapter 10 Delayed Interupt Module

345
Chapter 11 Interrupt Controller

349
Chapter 12 A/D Converter

365
- Overview of the A/D Converter
  366
- A/D Converter Registers
  368
- A/D Converter Operation
  376
- Precautions on the Using A/D Converter
  378
Chapter 13 Uart

379
Chapter 14 Dma Controller (Dmac)

403
- Overview of the DMA Controller (DMAC)
  404
- DMA Controller (DMAC) Registers
  406
- DMA Controller (DMAC) Operation
  425
  - Setting a Transfer Request
    428
  - Transfer Sequence
    430
  - General Aspects of DMA Transfer
    434
  - Addressing Mode
    436
  - Data Types
    437
  - Transfer Count Control
    438
  - CPU Control
    439
  - Hold Arbitration
    440
  - Operation from Starting to End/Stopping
    441
  - DMAC Interrupt Control
    445
  - Channel Selection and Control
    446
  - Supplement on External Pin and Internal Operation Timing
    448
- Operation Flowcharts
  452
- Data Bus
  455
- DMA External Interface
  458
  - Input Timing of the Dreqx Pin
    459
  - FR30 Compatible Mode of DACK
    461
Chapter 15 Bit Search Module

463
- Overview of the Bit Search Module
  464
- Bit Search Module Registers
  465
- Bit Search Module Operation
  467
Chapter 16 I 2 C Interface

469
- Overview of the I C Interface
  470
- I 2 C Interface Registers
  471
- Block Diagram of I 2 C Interface
  473
- Detailed on Registers of the I C Interface
  474
- I 2 C Interface Operation
  488
- Operation Flowcharts
  493

Fujitsu FR Family FR60 Lite User Manual (104 pages)

32-BIT MICROCONTROLLER bits pot red CAN motor board

Brand: Fujitsu | Category: Computer Hardware | Size: 2.49 MB

Fujitsu FR Family FR60 Lite User Manual (26 pages)

Brand: Fujitsu | Category: Adapter | Size: 0.56 MB

User Guide
1
Revision History

2
Warranty and Disclaimer

3
- Table of Contents
  4
- Contents
  
  4
1 Overview

5
- Abstract
  5
- General Description
  6
- Functional Restrictions
  7
2 Installation

9
3 Switches and Jumpers

10
4 Mechanical Dimensions

19
5 Cpld

20
- CPLD Verilog Code
  20
- CPLD Constraints
  22
- CPLD Programming Jumper (J491)
  22
6 Information in the Www

23
7 China-Rohs Regulation

24
8 Recycling

26

Fujitsu Categories

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More Fujitsu Manuals

Fujitsu FR Family FR60 Lite Manuals

Fujitsu FR Family FR60 Lite User Manual (1038 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 MB91460 Rev.a/Rev.b Overview

Chapter 3 MB91460 Series Basic Information

Chapter 4 CPU Architecture

Chapter 5 CPU Registers

Chapter 6 EIT: Exceptions, Interrupts and Traps

Chapter 7 Branch Instruction

Chapter 8 Device State Transition

Chapter 9 Reset

Chapter 10 Standby

Chapter 11 Memory Controller

Chapter 12 Instruction Cache

Chapter 13 Clock Control

Chapter 14 PLL Interface

Chapter 15 CAN Clock Prescaler

Chapter 16 Clock Supervisor

Chapter 17 Clock Modulator

Chapter 18 Timebase Counter

Chapter 19 Timebase Timer

Chapter 20 Software Watchdog Timer

Chapter 21 Hardware Watchdog Timer

Chapter 22 Main Oscillation Stabilisation Timer

Chapter 23 Sub Oscillation Stabilisation Timer

Chapter 24 Interrupt Control

Chapter 25 External Interrupt

Chapter 26 DMA Controller

Chapter 27 Delayed Interrupt

Chapter 28 Bit Search

Chapter 29 MPU / EDSU

Chapter 30 I/O Ports

Chapter 31 External Bus

Chapter 32 USART (LIN / FIFO)

Chapter 33 I2C Controller

Chapter 34 CAN Controller

Chapter 35 Free-Run Timer

Chapter 36 Input Capture

Chapter 37 Output Compare

Chapter 38 Reload Timer

Chapter 39 Programmable Pulse Generator

Chapter 40 Pulse Frequency Modulator

Chapter 41 Up/Down Counter

Chapter 42 Sound Generator

Chapter 43 Stepper Motor Controller

Chapter 44 A/D Converter

Fujitsu FR Family FR60 Lite Hardware Manual (664 pages)

Table of Contents

Chapter 1 Overview

Chapter 2 Handling the Device

Chapter 3 Cpu and Control Units

Chapter 4 External Bus Interface

Chapter 5 I/O Port

CHAPTER 6 8/16-Bit Up/Down Counters/Timer and U-Timers

Chapter 7 16-Bit Free-Running Timer and 16-Bit Reload Timer

Chapter 8 Programmable Pulse Generator (Ppg) Timer

Chapter 9 Interrupt Controller

Chapter 10 External Interrupt and Nmi Controller

Chapter 11 Realos-Related Hardware

Chapter 12 A/D Converter

Chapter 13 8-Bit D/A Converter

Chapter 14 Uart, Serial I/O Interface (Sio), Input Capture Module, and Output Compare Module

Chapter 15 I 2 C Interface

Chapter 16 Dma Controller (Dmac)

Fujitsu FR Family FR60 Lite Hardware Manual (636 pages)

Table of Contents

Chapter 1 Overview

Chapter 2 Handling the Device

Chapter 3 Cpu and Control Units

Chapter 4 External Bus Interface

Chapter 5 I/O Port

Chapter 6 16-Bit Reload Timer

Chapter 7 Ppg Timer

Chapter 8 U-Timer

Chapter 9 External Interrupt and Nmi Controller

Chapter 10 Delayed Interupt Module

Chapter 11 Interrupt Controller

Chapter 12 A/D Converter

Chapter 13 Uart