Operation Of I/O Extended Serial Interface - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE

18.3 Operation of I/O Extended Serial Interface

The I/O extended serial interface, which is used for input and output of eight-bit serial
data, consists of the SMCS register and SDR register.
■ Operation of I/O Extended Serial Interface
For input and output of serial data, the contents of the shift register are output at the serial
output pin (SOT0 and SOT1 pins) in bit series in synchronizing with the falling edge of a serial
shift clock (an external clock or internal clock). And they are input to the SDR register at serial
input pins (SIN0 and SIN1 pins) in bit series in synchronization with the rising edge. The
direction of shift (transfer from the MSB or LSB) can be specified with the BDS bit of the SMCS
register.
Upon completion of a transfer, the status changes to the suspend state or data register R/W
wait state depending on the MODE bit of the SMCS register. These states are changed back to
the transfer state in the following two ways.
• To recover from the suspend state, write "0" to the STOP bit and "1" to the STRT bit. (The
STOP and STRT bits can be set at the same time.)
• To recover from the SDR register R/W wait state, read or write to the data register.
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