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Table 6.2-2 Function Description of Each Bit of the Clock Monitor Register (CKMR) (2/2)
Bit name
bit 13
MCM:
Main Clock
Monitor bit
bit 14
PCM:
PLL Clock Monitor
bit
bit 15
SCM:
Sub Clock Monitor
bit
•
This bit indicates if the main oscillator is ready or not.
• MCM = "1" means that the main oscillator is ready and can be used. If MCM = "1"
although MCE was set to "0", then the Main oscillator has not been disabled because
the Main clock or PLL clock is used for System Clock 1 or 2.
• MCM = "0" means that the main oscillator is either disabled or the main oscillation
stabilization time is in effect.
• A Power or External reset (RST falling edge) and a Main clock stop detection reset
initializes this bit to "0". See section 8.3 Startup after Power and External reset for
more details regarding the effect of RST.
• A Sub clock stop detection, Software or Watchdog reset does not reset this bit.
Note:
The Main Clock Stabilization Time select bits CKSSR:MCST[2:0] are reset to "111"
18
(2
CLKMC cycles) by any reset. Hence if any reset is asserted within 2
cycles after activation of the Main oscillator, then MCM will be cleared to '0'.
•
This bit indicates if the PLL is ready or not.
• PCM = "1" means that the PLL clock is ready and can be used. If PCM = "1"
although PCE was set to "0", then the PLL has not been disabled because the PLL is
used for System Clock 1 or 2.
• PCM = "0" means that the PLL is either disabled or the PLL stabilization time is in
effect.
• Any reset initializes this bit to "0" (PLL disabled).
•
This bit indicates if the sub oscillator is ready or not.
• SCM = "1" means that the sub oscillator is ready and can be used. If SCM = "1"
although SCE was set to "0", then the Sub oscillator has not been disabled because
the Sub clock is used for System Clock 1 or 2.
• SCM = "0" means that the sub oscillator is either disabled or the sub oscillation
stabilization time is in effect.
• A Power or External reset and a Sub clock stop detection reset initializes this bit to
"0".
• A Main clock stop detection, Software or Watchdog reset does not reset this bit.
Note:
The Sub Clock Stabilization Time select bits CKSSR:SCST[1:0] are reset to "11"
16
(2
CLKSC cycles) by any reset. Hence if any reset is asserted within 2
cycles after activation of the Sub oscillator, then SCM will be cleared to '0'.
CHAPTER 6 CLOCKS
Function
18
CLKMC
16
CLKSC
155
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