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CHAPTER 21 400 kHz I
Table 21.2-2 Function of each bit of the bus control register (IBCRn) (2/2)
Bit name
bit 11
ACK:
Acknowledge bit
bit 10
GCAA:
General call
address
acknowledge bit
bit 9
INTE:
Interrupt enable
bit
bit 8
INT:
Interrupt flag bit
■ SCC, MSS and INT bit competition
Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to
generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as
follows:
• Next byte transfer and stop condition generation. When "0" is written to the INT bit and "0" is written to
the MSS bit, the MSS bit takes priority and a stop condition is generated.
• Repeated start condition generation and stop condition generation. When a "1" is written to the SCC bit
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2
C INTERFACE
This bit enables the acknowledge generation on data byte reception. It only can be
changed by the user.
"0": The interface will not acknowledge on data byte reception
"1": The interface will acknowledge on data byte reception
This bit is not valid when receiving address bytes in slave mode - if the interface detects
its 7 or 10 bit slave address, it will acknowledge if the corresponding enable bit (ENTB
in ITMK or ENSB in ISMK) is set.
Write access to this bit should occur during an interrupt (INT="1") or if the bus is idle
(BB="0" in the IBSR register) only.
This bit enables acknowledge generation when a general call address is received. It only
can be changed by the user.
"0": The interface will not acknowledge on general call address byte reception.
"1": The interface will acknowledge on general call address byte reception.
Write access to this bit should occur during an interrupt (INT="1") or if the bus is idle
(BB="0" in IBSR register) or the interface is disabled (EN="0" in ICCR register) only.
This bit enables the MCU interrupt generation. It only can be changed by the user.
"0": Interrupt disabled
"1": Interrupt enabled
Setting this bit to "1" enables MCU interrupt generation when the INT bit is set to "1"
(by the hardware).
This bit is the transfer end interrupt request flag. It is changed by the hardware and can
be cleared by the user. It always reads "1" in a Read-Modify-Write access.
Write access:
"0": Clear transfer end interrupt request flag
"1": No effect
Read access:
"0": Transfer not ended or not involved in current transfer or bus is idle
"1": Set at the end of a 1-byte data transfer or reception including the acknowledge bit
under the following conditions:
Device is bus master.
Device is addressed as slave.
General call address received.
Arbitration loss occurred.
Set at the end of an address data reception (after first byte if seven bit address
received, after second byte if ten bit address received) including the acknowledge
bit if the device is addressed as slave.
While this bit is "1" the SCL line will hold an "L" level signal. Writing "0" to this bit
clears the setting, releases the SCL line, and executes transfer of the next byte or a
repeated start or stop condition is generated. Additionally, this bit is cleared if a "1" is
written to the SCC bit or the MSS bit is being cleared.
Function
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